Multilevel Interconnect With Air-Gap Structure for Next-Generation Interconnections

Noguchi, J.; Oshima, Takayuki; Matsumoto, Toshimi; Uno, S.; Sato, Kazuo

doi:10.1109/ted.2009.2030538

Cited by 15 publications

(7 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Then, the pinch-off point to close the AG becomes higher, resulting in the risk of contact with the trench bottom of the upper metal level. Second, the AG is prohibited beside the upper via [11][12][13][14]. If a part of the via bottom is outside of the metal line because of size and overlay variation, the via hole is connected to the AG cavity.…”

Section: Design Restrictionsmentioning

confidence: 99%

“…The ultimate solution for a low k-value is the exclusion of all materials from the IMD, which is called an air gap (AG). There are two types of AG processes: (1) removal of the sacrificial material via thermal decomposition or chemical treatment [6][7][8][9][10] through the upper dielectric layer and (2) etching back the IMD followed by pinch-off of the next IMD deposition [11][12][13][14][15]. In the latter case, the AG can be formed selectively at the critical path, leaving dielectric materials in other places, which can retain the mechanical strength.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

2019

View full text Add to dashboard Cite

Air-gap (AG) technology on back-end-of-line (BEOL) provides a means to improve performance without area or power degradation. However, the “blind” use of AG based on traditional design methodologies does not provide sufficient performance gain. We developed an AG-aware design methodology to maximize performance gain with minimum cost. The experimental results of the proposed methodology, which was tested using a 10 nm Advanced RISC Machine (ARM) Cortex-A9 quad-core central processing unit (CPU), indicated a performance gain of 6.1–8.4% compared with traditional AG design. The performance gain achieved represents about half of the 10–15% performance improvement under the same power by a process node shrink. A Si process of consecutive double AG layers was developed by overcoming various process challenges, such as AG depth control, Cu/ultra-low-k damage, the hermetic AG liner, and step-height control above the AG. Furthermore, the capacitance was reduced by 17.0%, which satisfied the target goal in the simulation stage for the assumed structure. The optimized integration process was validated according to the function yield of the CPU, which was comparable to that of a non-AG process. The time-dependent dielectric breakdown and electromigration lifetime of the AG wire satisfied the 10-year criteria, and the assembly yield was verified.

show abstract

Section: Design Restrictionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

2019

View full text Add to dashboard Cite

show abstract

“…The lower limit of porous low-k reliability due to this reliability constraint is k $ 2.3 [98,99]. To attain lower effective k, structures such as air gaps are being actively studied [100,101].…”

Section: Time-dependent Breakdown Of Interlevel Dielectricsmentioning

confidence: 99%

Reliability of silicon integrated circuits

Oates

2015

Reliability Characterisation of Electrical and Electronic Systems

View full text Add to dashboard Cite

“…Previous reports have explored the role of air-gap structures in lowering line capacitance [3][4][5][6][7][8][9]. When depositing SiO 2 , air-gaps or voids can be formed between metal lines.…”

Section: Background 21 Capacitance Reduction Using Air Gap Structuresmentioning

confidence: 99%

“…Several processing techniques have been disclosed for forming air-isolation in electronic devices including the use of CMP and via etch [4], etch back technique [7][8], sacrificial polymers [5,6,[10][11][12][13], and wet etching [9]. Among these techniques, the use of a sacrificial polymer for creation of air-gaps is a promising method which can be applied to a variety of applications.…”

Section: Fabrication Of Air-gap Structuresmentioning

confidence: 99%

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

View full text Add to dashboard Cite

In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical-horizontal transitions. The motivation is to create an air-gap technology that offers the lowest possible effective k-value and near zero loss tangent minimizing the dielectric loss. The design and modeling of air-gap interconnection is presented. The fabrication challenges in airclad interconnect lines are discussed. A monolithic inverted air-gap horizontal transmission line structure is proposed as a means for further decreasing the dielectric loss. Extension of air-clad TSV technology for optical transmission is briefly discussed. IntroductionModern electronic systems are composed of a dense fabric of interconnect lines that connect electronic devices and chips. The scaling of transistors has resulted in miniaturization of individual devices and their interconnects. Smaller crosssectional area of electrical interconnects results in higher signal attenuation and makes data and clock recovery complex. High-speed interconnects have two primary loss mechanisms, namely metallic skin effect losses and dielectric losses. Skin effect loss is a phenomenon where, at high frequencies, the current is crowded into the near-surface region of the metal around the periphery of the conductor. As a result, the effective AC resistance per unit length of conductor increases with frequency. The second loss mechanism deals with dielectric losses. Dielectric losses are directly proportional to frequency and are therefore more pronounced at higher frequencies. Also, resistive losses in the return ground path cannot be ignored and are determined by the geometry and materials constituting the return path. Overall, dielectric losses dominate at frequencies above several GHz [1-2], as shown in Figure 1. This figure was produced with data from the International Technology Roadmap for Semiconductors (ITRS) for signal frequencies up to 50 GHz. As shown in Figure 1, the dielectric loss is more than twice that of the conductor loss at 20 GHz and the dielectric loss becomes more dominant at frequencies above 20 GHz. Thus, in order to achieve meaningful reduction in signal attenuation it is important to find ways to mitigate the dielectric loss at high frequencies. One way of achieving this goal is to use better interconnect and substrate materials.

show abstract

Multilevel Interconnect With Air-Gap Structure for Next-Generation Interconnections

Cited by 15 publications

References 12 publications

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers

Reliability of silicon integrated circuits

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Contact Info

Product

Resources

About