Multiple continuous error correct code for high performance network-on-chip

Wang, Bin; Xie, Jing; Mao, Zhigang; Wang, Qin

doi:10.1109/primeasia.2011.6075080

Cited by 9 publications

(5 citation statements)

References 7 publications

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“…In (17), all correctable error bit patterns up to 5 bits are considered. The probability of random residual error of MECCRLB scheme for correcting up to 5 random error bits is considered as This work is licensed under a Creative Commons Attribution 4.0 License.…”

Section: Performance Estimation Methodologies Of Tec Coding Schemmentioning

confidence: 99%

“…Wang et.al. [17] developed Multiple Continuous Error Correct Coding (MCECC) scheme to reinforce burst error correction. This supports burst error correction of up to 14 continuous error bits.…”

Section: Related Workmentioning

confidence: 99%

“…P re is evaluated for TEC, MECCRLB and HPC coding schemes for correction of up to 5 random error bits using (17), (18) and (19), respectively, for different values of σ and is shown in Fig. 16.…”

Section: B Reliability Evaluationmentioning

confidence: 99%

“…MECCRLB scheme has lower P re then TEC and HPC, as it corrects random errors present in 32 bit flit and 15 redundant bits. Using (17), P re is estimated and validated through simulations. In the simulation environment, three standard video bit stream benchmarks, football, foreman and mobile are applied to H.264 encoder based JM 15.1 simulator [34] to extract the bit streams.…”

Section: B Reliability Evaluationmentioning

confidence: 99%

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Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

2020

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Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks. ECC significantly improves reliability of NoC interconnects with area and power overhead. In this paper, we propose a novel Transient Error Correction (TEC) coding scheme for reliable low power data link layer in NoC to attain a high error correction capability with less hardware overhead. Performance of TEC scheme is evaluated with realistic traffic patterns and validated with simulation results. The proposed scheme has less residual errors than the Hamming product code enabling reliable transmission at lower link swing voltage. Further, the scheme reduces the power consumption of NoC interconnects up to 71% as compared to Hamming product code with a marginal increase in codec delay and thus router delay. TEC scheme performs well in high noise environment with no delay penalty associated with retransmission. INDEX TERMS Network on Chip, Error correcting codes, Reliability, On-chip interconnects, Hamming code.

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Section: Performance Estimation Methodologies Of Tec Coding Schemmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: B Reliability Evaluationmentioning

confidence: 99%

Section: B Reliability Evaluationmentioning

confidence: 99%

See 2 more Smart Citations

Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC

2020

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“…Crosstalk avoidance random burst error detection and correction (CARBEDC) code [3] and crosstalk avoidance enhanced double error correction (CAEDEC) code [41] were proposed for multi‐bit error correction, but they could correct only two‐ and three‐bit errors. The authors proposed multiple continuous error correct coding (MCECC) [42] that could correct the only continuous error to 14 bits and reduce 50% crosstalk effect with a suitable design. Joint crosstalk‐aware multiple error correction (JMEC) [43] with the interleaving technique was proposed, and it was a combination of odd‐weight‐column and duplication.…”

Section: Existing Error Control Methods For On‐chip Interconnectsmentioning

confidence: 99%