Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)

Abstract

Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies also implement logic functionalities uncommon to traditional technologies that can be beneficial to existing CMOS architectures. In this work, we study how plasmonic-based devices can complement CMOS technology to achieve a more efficient implementation of multiplier architectures, which are the core of state-of-the-art data-and signal-processing circuits. A critical part of modern multipliers is the partial-product reduction step, used to reduce the partial product tree into a 2-input addition. In CMOS technology, this step is achieved by using compact and fast counters. On the other hand, the proposed plasmonic cells naturally implement counters of 3-, 9-and 27-inputs within a few logic levels at ultra-high speed. Thus, we present novel multiplier architectures, which take advantage of large plasmonicbased counters to reduce the number of cells and logic levels in the partial product reduction step of the multiplication. Our experimental results show that 3 levels and 30 counters are needed when 27-input cells are used. On the other side, 6 levels and 72 counters are employed with 9-input cells. Finally, we present various 16 × 16 multiplier implementations mixing 9-and 27input cells, focusing on the trade-off in the number of counters, levels, and area of each architecture.

Comparison of Photonic to Plasmonic Mode Converters for Plasmonic Multiple-Input Devices

“…LOGIC GATE To design the mode converter for multiple-input plasmonic devices, we take a multi-functional plasmonic logic gate as an example. The nanoscale cascadable plasmonic logic gate was previously designed [9], and its application to implement arithmetic primitives like multipliers was demonstrated [23]. The logic gate can have 3, 9, or 27 inputs.…”

Plasmonic MIM and MSM Waveguide Couplers for Plasmonic Integrated Computing System

“…Note that, although plasmonic MIM WGs are lossy (< 10µm propagation length), we focus on very compact devices like the ultra-high throughput majority gate [36]. Such a gate can implement many functions by simply adjusting the threshold voltage of the CMOS receiver [47], which would be impossible to achieve with CMOS and would require many transistors while still operating at much lower frequencies. We emphasize that although in this work, we consider plasmonic MIM logic gate for demonstrating the system-level performance of the couplers, the couplers are applicable for coupling any MIM WG-based devices [15]- [25] with the MSM WG.…”

Modeling and Optimization of Plasmonic Detectors for Beyond-CMOS Plasmonic Majority Logic Gates

“…The majority gate structure under consideration can implement all Boolean functionality also. Additionally, the MIM waveguide structure with some extension can realize the socalled threshold logic and can then be used as a building block for counters and multipliers, which we discussed in another work [40]. However, the logic structure cannot operate alone and the optical output needs to be converted to the electrical domain for data interpretation.…”