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In this work, we report the modeling and design of a high-speed Ge-based plasmonic detector coupled with a Metal-Insulator-Metal (MIM) plasmonic majority gate. The detector is designed to distinguish between multiple output levels of the integrated majority gate. Through numerical analyses we predict the proposed plasmonic detector has an intrinsic bandwidth beyond 220GHz at an applied bias of only 100mV . An asymmetric Metal-Semiconductor-Metal (MSM) configuration of the plasmonic detector ensures a dark current of a few nA which results in high sensitivity. The high electric field generated by the electrode asymmetry enables effective separation of the photogenerated carriers resulting in high photocurrent even at few mVs of applied bias. The low capacitance of less than 1f F arising from the small detector dimensions results in a high RClimited bandwidth. Moreover, the narrow plasmonic Ge slot of the photodetector provides a short drift path and fast transit time for carriers. Unlike previously reported plasmonic detectors that use noble metals as electrodes, our proposed detector employs Al and Cu to meet CMOS compatibility requirements and thus can be a potential candidate for high-speed computational systems in industry-level applications. Additionally, the findings presented in the paper will be helpful for the future realization of an integrated plasmonic system.

The work focuses on optimizing the device parameters of a Si‐based dual‐material double‐gate tunnel field‐effect transistor for maximizing its efficiency. The efficiency is measured in terms of drain current, subthreshold swing, ION/IOFF ratio, and electron concentration in Si body. A numerical model of dual‐material double‐gate tunnel field‐effect transistor is developed using Silvaco, Atlas. Simulations are performed in Technology Computer Aided Design (TCAD) using Kane's band‐to‐band tunneling model. Based on the simulation results, optimum values of gate workfunctions, doping levels in different regions, ratio of gate lengths, and Si body thickness are suggested for the device. The proposed optimized device shows subthreshold swing of 15 − 41mV/dec, on current of 1.4 × 10 − 4A/μm and ION/IOFF ratio on the order of 1012.

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Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies also implement logic functionalities uncommon to traditional technologies that can be beneficial to existing CMOS architectures. In this work, we study how plasmonic-based devices can complement CMOS technology to achieve a more efficient implementation of multiplier architectures, which are the core of state-of-the-art data-and signal-processing circuits. A critical part of modern multipliers is the partial-product reduction step, used to reduce the partial product tree into a 2-input addition. In CMOS technology, this step is achieved by using compact and fast counters. On the other hand, the proposed plasmonic cells naturally implement counters of 3-, 9-and 27-inputs within a few logic levels at ultra-high speed. Thus, we present novel multiplier architectures, which take advantage of large plasmonicbased counters to reduce the number of cells and logic levels in the partial product reduction step of the multiplication. Our experimental results show that 3 levels and 30 counters are needed when 27-input cells are used. On the other side, 6 levels and 72 counters are employed with 9-input cells. Finally, we present various 16 × 16 multiplier implementations mixing 9-and 27input cells, focusing on the trade-off in the number of counters, levels, and area of each architecture.