Multiprocessor Clustering for Embedded Systems

Kianzad, Vida; Bhattacharyya, Shuvra S.

doi:10.1007/3-540-44681-8_99

Cited by 8 publications

(12 citation statements)

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“…The clusterization function representation is a mechanism for encoding candidate clustering solutions that is amenable to probabilistic search strategies, perhaps most notably to genetic algorithms, but that avoids the asymmetries and repair requirements that plague the effectiveness of conventional solution encodings that are used during scheduling [8]. The clusterization function concept is captured by the following definition.…”

Section: Clusterization Function Representationsmentioning

confidence: 99%

“…In this approach, the initial genetic algorithm population is initialized with a random selection of clusterization functions (mappings from E into f0; 1g) and the fitness is evaluated using a modified version of list scheduling that abandons the restrictions imposed by a global scheduling clock, as proposed in [16].This application of the clusterization function has been shown to significantly outperform existing clustering techniques, including the internalization algorithm, the dominant sequence algorithm, and randomized versions of the internalization and dominant sequence algorithms that were evaluated under equal amounts of synthesis time (equal amounts of time available for probabilistic search) [8]. …”

Section: Definitionmentioning

confidence: 99%

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Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Bambha¹,

Kianzad²,

Khandelia³

et al. 2002

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Abstract. Self-timed scheduling is an attractive implementation style for multiprocessor DSP systems due to its ability to exploit predictability in application behavior, its avoidance of over-constrained synchronization, and its simplified clocking requirements. However, analysis and optimization of selftimed systems under real-time constraints is challenging due to the complex, irregular dynamics of selftimed operation. In this paper, we review a number of high-level intermediate representations for compiling dataflow programs onto self-timed DSP platforms, including representations for modeling the placement of interprocessor communication (IPC) operations; separating synchronization from data transfer during IPC; modeling and optimizing linear orderings of communication operations; performing accurate design space exploration under communication resource contention; and exploring alternative processor assignments during the synthesis process. We review the structure of these representations, and discuss efficient techniques that operate on them to streamline scheduling, communication synthesis, and power management of multiprocessor DSP implementations.

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Section: Clusterization Function Representationsmentioning

confidence: 99%

Section: Definitionmentioning

confidence: 99%

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Bambha¹,

Kianzad²,

Khandelia³

et al. 2002

Self Cite

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“…However, these approaches typically have complex solution representations in the underlying genetic algorithm formulation, and require "repair" mechanisms that further reduce their search efficiency. The clusterization function representation is a mechanism for encoding candidate clustering solutions that is amenable to probabilistic search strategies, perhaps most notably to genetic algorithms, but that avoids the asymmetries and repair requirements that plague the effectiveness of conventional solution encodings that are used during scheduling [7]. The clusterization function concept is captured by the following definition.…”

Section: Clusterization Function Representationsmentioning

confidence: 99%

“…In this approach, the initial genetic algorithm population is initialized with a random selection of clusterization functions (mappings from into ) and the fitness is evaluated using a modified version of list scheduling that abandons the restrictions imposed by a global scheduling clock, as proposed in [13]. This application of the clusterization function has been shown to significantly outperform existing clustering techniques, including the internalization algorithm, the dominant sequence algorithm, and randomized versions of the internalization and dominant sequence algorithms that were evaluated under equal amounts of synthesis time (equal amounts of time available for probabilistic search) [7].…”

Section: Definitionmentioning

confidence: 99%

Mapping DSP Applications onto Self-timed Multiprocessors

Bhattacharyya¹,

Bambha²,

Khandelia³

et al. 2001

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BackgroundMultiprocessor implementation of DSP applications involves the interaction of several complex factors including scheduling, interprocessor communication, synchronization, iterative execution, and more recently, voltage scaling for low power implementation. Addressing any one of these factors in isolation is itself typically intractable in any optimal sense; at the same time, with the increasing trend toward multi-objective implementation criteria in the synthesis of embedded software, it is desirable to understand the joint impact of these factors. In this paper, we examine several high-level, intermediate representations that have been developed to analyze and optimize various multiprocessor DSP implementation factors and manage their interactions.The techniques discussed in this paper pertain to system specifications based on iterative synchronous dataflow (SDF) graphs [9]. Iterative SDF programming of DSP applications has been researched widely in the context of multiprocessor implementation, and numerous commercial DSP tools have been developed that incorporate SDF semantics. Examples of such tools include SPW by Cadence, COSSAP by Synopsys, and ADS by Hewlett-Packard.In SDF, an application is represented as a directed graph in which vertices (actors) represent computational tasks, edges specify data dependences, and the numbers of data values (tokens) produced and consumed by each actor is fixed. Delays on SDF edges represent initial tokens, and specify dependencies between iterations of the actors in iterative execution. For example, if tokens produced by the th invocation of actor are consumed by the th invocation of actor , then the edge contains two delays. Actors can be of arbitrary complexity. In DSP design environments, they typically range in complexity from basic operations such as addition or subtraction to signal processing subsystems such as FFT units and adaptive filters. We refer to an SDF representation of an applications an application graph.In this paper, we use a form of SDF called homogeneous SDF (HSDF) that is suitable for dataflow-based multiprocessor design tools. In HSDF, each actor transfers a single token to/from each incident edge. General techniques for converting SDF graphs into HSDF are developed in [9]. We refer to a homogeneous SDF graph as a dataflow graph (DFG). We represent a DFG by an ordered pair , where is the set of actors and is the set of edges. We refer to the source and sink actors of a DFG edge by and , we denote the delay on by , and we frequently represent by the ordered pair . We say that is an output edge of ; is an input edge of ; and is delayless if . The execution time or estimated execution time of an actor is denoted . Mapping an application graph onto a multiprocessor architecture includes three important steps -assigning actors to processors (processor assignment), ordering the actors assigned to each processor (actor ordering), and determining when each actor should commence execution. All of these tasks can either be performed at run...

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“…In contrast, multiprocessor mapping strategies for general purpose systems are typically designed with low to moderate complexity as a constraint [23]. Based on this observation, we took a new look at the two-step decomposition of scheduling in the context of embedded systems and developed an efficient evolutionary-based clustering algorithm (called CFA) that was shown to outperform the other leading clustering algorithms [10]. We also introduced a randomization approach to be applied to deterministic algorithms so they can exploit increases in additional computational resources (compile time tolerance) to explore larger segments of the solution space.…”

Section: Introductionmentioning

confidence: 99%

Efficient techniques for clustering and scheduling onto embedded multiprocessors

Kianzad

Bhattacharyya

2006

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Multiprocessor mapping and scheduling algorithms have been extensively studied over the past few decades and have been tackled from different perspectives. In the late 1980's, the two-step decomposition of scheduling-into clustering and clusterscheduling-was introduced. Ever since, several clustering and merging algorithms have been proposed and individually reported to be efficient. However, it is not clear how effective they are and how well they compare against single-step scheduling algorithms or other multistep algorithms. In this paper, we explore the effectiveness of the two-phase decomposition of scheduling and describe efficient and novel techniques that aggressively streamline interprocessor communications and can be tuned to exploit the significantly longer compilation time that is available to embedded system designers. We evaluate a number of leading clustering and merging algorithms using a set of benchmarks with diverse structures. We present an experimental setup for comparing the single-step against the two-step scheduling approach. We determine the importance of different steps in scheduling and the effect of different steps on overall schedule performance and show that the decomposition of the scheduling process indeed improves the overall performance. We also show that the quality of the solutions depends on the quality of the clusters generated in the clustering step. Based on the results, we also discuss why the parallel time metric in the clustering step may not provide an accurate measure for the final performance of cluster-scheduling.

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Multiprocessor Clustering for Embedded Systems

Cited by 8 publications

References 8 publications

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Intermediate Representations for Design Automation of Multiprocessor DSP Systems

Mapping DSP Applications onto Self-timed Multiprocessors

Efficient techniques for clustering and scheduling onto embedded multiprocessors

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