Nano-power subthreshold current-mode logic in sub-100 nm technologies

Cannillo, F.; Toumazou, C.

doi:10.1049/el:20053082

Cited by 15 publications

(8 citation statements)

References 6 publications

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“…In [7], utilization of the finite output impedance of very short-channel PMOS load devices biased in saturation is proposed as means to achieve the desired large resistance. However, more studies are needed for exploring the matching properties of output impedance of MOS devices.…”

Section: A MCML Topologymentioning

confidence: 99%

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Tajalli

Vittoz

Leblebici

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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Abstract-This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 µm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

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Section: A MCML Topologymentioning

confidence: 99%

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Tajalli

Vittoz

Leblebici

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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“…This paper explores performance comparison of two source coupled logic structures with previously available Sub Threshold Source Coupled Logic (STSCL) gates for implementing ultra-low-power digital systems. In this approach, the power consumption and maximum speed of operation can be adjusted linearly through the tail bias current of each gate over a very wide range [11,12], thus, efficiently decoupling the decision of output voltage swing from power dissipation and delay. To enable the operation at very low trail bias current and to achieve the desired performance, we have to use a special circuit technique for implementing very low power Source Coupled Logic circuit.…”

Section: Introductionmentioning

confidence: 99%

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Rai¹,

Mishra²,

Tiwari³

2013

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This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 µm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

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“…In [20], the intrinsically limited output impedance of deep-submicron, short-channel pMOS devices has been used to implement very high value load resistances for SCL topology. Here, a more general approach with much less sensitivity to process and technology variations will be introduced [19].…”

Section: Introductionmentioning

confidence: 99%

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Tajalli

Brauer

Leblebici

et al. 2008

IEEE J. Solid-State Circuits

106

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Abstract-This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.

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Nano-power subthreshold current-mode logic in sub-100 nm technologies

Cited by 15 publications

References 6 publications

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

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