NanoBridge-Based FPGA in High-Temperature Environments

Miyamura, Miharu; Sakamoto, Toshitsugu; Bai, Xu; Tsuji, Yoshiyuki; Morioka, A.; Nebashi, R.; Tada, Munehiro; Banno, Naoki; Okamoto, K.; Iguchi, N.; Hada, H.; Sugibayashi, Toshio; Nagamatsu, Yuya; Ookubo, Soichi; Shirai, Tomoyuki; Sugai, Fumihito; Inaba, Masayuki

doi:10.1109/mm.2017.3711648

Cited by 12 publications

(13 citation statements)

References 18 publications

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“…By developing the FPGA board with more suitable resource utilization for the ADPLL, the advantage of the FPGA emulation can be more obvious. In addition, considering the future of FPGA technology [26,27], which can contribute to filling the gap between FPGA and ASIC, the FPGA implementation of ADPLL also has feasibility as a real-operating PLL design.…”

Section: Discussionmentioning

confidence: 99%

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

2019

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This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the standard cell library, thus making the design portable andreducing the time required to fit for different semiconductor processes considerably. Implementedring-DCO has a wide tuning range and high-frequency resolution which meet the demands ofsystem-level integration. The ADPLL implemented in this work has the characteristics of designflexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast responsefor achieving a locked state. The proposed ADPLL can be easily ported to different processes ina short time. The design adaptation cost is limited to adjustment of loop parameters in the code.Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable forSystem-on-Chip (SoC) applications.

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Section: Discussionmentioning

confidence: 99%

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

2019

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“…(b) Illustration of the CAS-based routing MUX [11], [12]. (c) Schematic of a unit logic tile (details are described in [13]). the n-type transistor connected to the middle node of CAS so as to control the on conductance.…”

Section: As-fpgamentioning

confidence: 99%

Single-Event Effects Induced on Atom Switch-based Field-Programmable Gate Array

Takeuchi

Sakamoto

Tada

et al. 2019

IEEE Trans. Nucl. Sci.

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Single-event effects (SEEs) of atom switches (ASs) embedded on 40-nm complementary metal-oxide-semiconductor (CMOS) are investigated with both heavy-ion and pulsed laser irradiation. In the evaluation of an AS-based field-programmable gate array (AS-FPGA), ASs show immunity against the irradiation and there is no change of the state of ASs both in a crossbar switch and memory in lookup tables (LUTs). ASs are not supposed to make any single-event transient (SET) noise when the ions hit. However, the CMOS layer shows SETs, and new approaches are proposed to solve the SET in CMOS, especially for AS-FPGA application. Index Terms-Atom switch (AS), heavy ions, pulsed laser, single-event effects (SEEs), single-event transient (SET).

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“…Scaling down of nodes creates single-event upset (SEU) or soft error problem and large current leakage which shows high temperature dependence. A nanobridge-based FPGA is presented in [18] to address the problem of high temperature environment which is nonvolatile, SEU-free and have the structure of complementary atom switch (CAS) exhibiting reliable OFF state and low voltage.…”

Section: Fpga With Cross-bar Switchesmentioning

confidence: 99%

“…Whereas, for SCR devices, changing its turnon voltage requires alteration of design parameters [8]. MEMS FPGAs also have simpler architecture [18]. It is also shown that MEMS can be used for power gating to VLSI chip [19].…”

Section: Introductionmentioning

confidence: 99%

Back-end-of-the-line MEMS switches for power management, ESD and security

Tazin¹,

Saab²,

Tabib-Azar³

2018

Preprint

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This paper discusses a MEMS switch that can be fabricated using low temperature (<100oC) deposition and patterning techniques suitable for the back-end-of-the-line integration with CMOS. The resulting cross-bar switches can be used for electrostatic discharge protection, FPGA implementation, chip security assessment and lock-down, and circuit block power management. We discuss platinum and iron switch with turn-on voltages of ~ 1.8 V. In the case of the iron switches, we also show that they can be magnetized to have “memory” and stay on when turned on. Platinum switch cycling of up to 1000 times did not show any changes in their turn-on voltage and their contact resistance was unchanged. The 10-100 nm switch airgaps were formed using low temperature sputtered sacrificial polysilicon and XeF2 etching. XeF2 does not attack any of the metals used in CMOS enabling fabrication of cross-bar switches with any of these metals. Once activated, it takes ∿ 6  to mechanically turn on the switch that can be decreased to ~1 ns by optimizing the device structure. Interestingly, the nm-scale gaps can be used as spark gap as a fast plasma switch to discharge first followed by the activation of the MEMS switch.

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NanoBridge-Based FPGA in High-Temperature Environments

Cited by 12 publications

References 18 publications

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Single-Event Effects Induced on Atom Switch-based Field-Programmable Gate Array

Back-end-of-the-line MEMS switches for power management, ESD and security

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