Nanoscale Memory Repair

Abstract

), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights.Printed on acid-free paper Springer is part of Springer ScienceþBusiness Media (www.springer.com) PrefaceRepair techniques for nanoscale memories are becoming more important to cope with ever-increasing "errors" causing degraded yield and reliability. In fact, without repair techniques, even modern CMOS LSIs, such as MPUs/SoCs, in which memories have dominated the area and performances, could not have been successfully designed. Indeed, various kinds of errors have been prominent with larger capacity, smaller feature size, and lower voltage operations of such LSIs. The errors are categorized as hard/soft errors, timing/voltage margin errors, and speed-relevant errors. Hard/soft errors and timing/voltage margin errors, which occur in a chip, are prominent in a memory array because the array comprises memory cells having the smallest size and largest circuit count in the chip. In particular, coping with the margin errors is vital for low-voltage nanoscale LSIs, since the errors rapidly increase with device and voltage scaling. Increase in operating voltage is one of the best ways to tackle the issue. However, this approach is unacceptable due to intolerably increased power dissipation, calling for other solutions by means of devices and circuits. Speed-relevant errors, which are prominent at a lower voltage operation, comprise speed-degradation errors of the chip itself and intolerably wide chip-to-chip speed-variation errors caused by the ever-larger interdie designparameter variation. They must also be solved with innovative devices and circuits. For the LSI industry, in order to flourish and proliferate, the problems must be solved based on in-depth investigation of the errors.Despite the importance, there are few authoritative books on repair techniques because the solutions to the problems lie across different fields, e.g., mathematics and engineering, logic and memories, and circuits and devices. This book systematically describes the issues, based on the authors' long careers in developing memories and low-voltage CMOS circuits. This book is intended for both students and engineers who are interested in the yield, reliability, and low-voltage operation of nanoscale memories. Moreover, it is instructive not only to memory designers, but also to all digital and mixed-signal LSI designers who are at the leading edge of such LSI developments.Chapter 1 describes the basics of repair techniques. First, after categorizing sources of hard/soft errors, the reductions by means of redundancy, error checking v an...

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

“…Referring back to Figure 2 (Section 2.1), the i th "row" of a rank is formed by taking the i th row in each chip and concatenating them. But if the row in one of the chips is faulty, the manufacturer re-maps it to a spare row (e.g., i j ) [28]. In this case, the i th "row" has four immediate neighbors: i˙1 th rows in seven chips and j˙1 th rows in the re-mapped chip.…”

“…Interestingly, the two 14Figure 9 presents further indications of re-mapping, where some modules have non-zero values for˙8 or beyond. Such large differences -which in some cases reach into the thousands -may be caused when a faulty row is re-mapped to a spare row that is far away, which is typically the case [28]. victim cells in module B 11 with two aggressor rows were also the same cells that had errors for both runs of the test pair described in Section 6.1.…”

“…Retire cells (manufacturer). Before DRAM chips are sold, the manufacturer could identify victim cells and re-map them to spare cells [28]. However, an exhaustive search for all victim cells could take several days or more (Section 7).…”

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

“…Redundancy repair techniques are widely employed in modern DRAM systems to recover from various faults and to prevent system failures [1,2,3,4]. Such repair techniques are designed to substitute spare elements for faulty elements, particularly permanent faults due to manufacturing defects.…”

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair

“…Next, we discuss how the combined approach changes ways to treat memory errors. Memory errors are classified as either hard or soft errors [3]. Hard errors are errors caused by permanent hardware faults.…”