Nanoscale probing of dielectric breakdown at SiO2/3C-SiC interfaces

Abstract

Thin (6–7 nm) SiO2 layers were thermally grown onto cubic silicon carbide (3C-SiC) heteroepitaxial layers of different surface roughness and with different types of near-surface epitaxial defects. Localized dielectric breakdown (BD) was studied by electrically stressing the system using conductive atomic force microscopy (C-AFM), which constitutes a means to directly and simultaneously observe localized dielectric failure as a function of stress time and surface morphology with nanoscale lateral resolution. AFM and scanning capacitance microscopy (SCM) were used to monitor defects and the morphological and capacitive uniformities of the SiO2, respectively, while capacitance-voltage (C-V) measurements were used to evaluate the presence of charges and traps in the oxide layers. The BD kinetics was evaluated by fitting the experimental failure ratios as a function of the stress time to the failure probability described by Weibull statistics, in turn allowing a distinction to be made between defect-induced (extrinsic) and intrinsic dielectric BD events. The results give useful information about how morphological features at the 3C-SiC surface as well as trapped charges influence the BD generation in thermally grown oxides on this polytype.

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

“…2b). To explore the electrical behaviour of the TD, a nanoscale electrical characterization was carried out using the conductive atomic force microscopy (C-AFM) [18]. In particular, C-AFM allowed determining the morphological shape of the surface (Fig.…”

“…In particular, C-AFM allowed determining the morphological shape of the surface (Fig. 4a) -a triangle with the vertex in the [11][12][13][14][15][16][17][18][19][20] direction -about 25 nm deeper than the surface of the JFET region where it is located. Even in the triangular region (highlighted with a dashed line), the surface conductivity is rather homogeneous (Fig.…”

“…3) allowed to identify a threading dislocation (TD) running along the epitaxial layer. The TEM dual beam investigation -along the directions[11][12][13][14][15][16][17][18][19][20] and [0002], shown in Figs. 3a and 3b, demonstrated the presence of a mixed dislocation.…”

A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

“…In a strong inversion case such as the MOSFET being switched on, ΦB≈∆EC [4]. The theoretical value of ∆EC for 4H-SiC/SiO2 is 2.7 eV and had recently been experimentally reported [15], whereas the value for Si is 3.2 eV, and for 3C-SiC 3.7 eV [16], potentially the most stable among the three. Moreover, the smaller bandgap means most of the traps troubling the 4H-SiC/SiO2 interface are located in the conduction band of 3C-SiC, namely not contributing to degrade the channel mobility, thus lower channel resistance for a MOSFET.…”

“…Regarding the 3C-SiC/SiO2 interface, some study was performed on the interface trap density [33,34] and channel mobility [29,35,36], whereas very little on the reliability. In [16], dielectric breakdown of very thin (6-7 nm) and small area (100 nm diameter) thermally grown SiO2 on 3C-SiC(111) was studied by Time Dependent Dielectric Breakdown (TDDB) test at 10 V (≈15 MV/cm), and Weibull slope β values of 4.4-5.1 were obtained. This is close to the performance of SiO2 layers on Si with similar thickness.…”