2006
DOI: 10.1016/j.spmi.2005.08.020
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Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects

Abstract: Abstract-Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.

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Cited by 23 publications
(12 citation statements)
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“…«ростовые» деформационные поля, которые возникают вследствие различия постоянных кристаллической решетки (a) и температурных коэффициентов линейного расширения ( ) слоя и подложки [15][16][17][18][19]. Яр-ким примером практического использования ростовых деформаций является применение напряженных слоев Si и SiGe для увеличения по-движности носителей или создания инверсной заселенности в лазерных структурах.…”
Section: Discussionunclassified
“…«ростовые» деформационные поля, которые возникают вследствие различия постоянных кристаллической решетки (a) и температурных коэффициентов линейного расширения ( ) слоя и подложки [15][16][17][18][19]. Яр-ким примером практического использования ростовых деформаций является применение напряженных слоев Si и SiGe для увеличения по-движности носителей или создания инверсной заселенности в лазерных структурах.…”
Section: Discussionunclassified
“…Therefore, numerous researchers have conducted extensive and in-depth research on SOI devices in recent years. [11][12][13] For the purpose of reducing the leakage current and improving SCEs of the SOI MOSFET, our focus is on modifying the channel potential distribution to better control channel conduction when the device is operated in the subthreshold region. As is known to all, an effective method for reducing a disadvantageous SCEs is doped the channel with a higher dose of impurities.…”
Section: Introductionmentioning
confidence: 99%
“…An example of the efficient application of growth-induced strains is given by CMOS transistors, in which the substantial deformations in the channel region are obtained by combining strained Si and SiGe layers. As a result, the mobility of charge carriers increases [1,2]. A substantial improvement of light-emitting characteristics is observed at low excitation levels for quantum wells fabricated on the basis of A 3 B 5 compounds and compressively stressed in the heterojunction plane, which occurs owing to the creation of conditions for inverse level population [3].…”
Section: Introductionmentioning
confidence: 99%