Nanostructured porous silicon as thick electrical insulator for radio‐frequency applications

Abstract

Nanostructured porous silicon layers are studied for the purpose of their use as electrical insulators between mono‐crystalline silicon substrates and integrated planar radio frequency (rf) devices. The capacitive nature of the layers with a tangent loss lower than 10–2 is demonstrated in the 105–109 Hz range by means of complex impedance measurements and rf regime experiments on micro L –C resonant circuits. Finally, the insulating capabilities of nanostructured porous silicon were evaluated using numerical simulations combined with our experimental data. A minor contribution of the porous silicon residual conductance to the rf energy loss is found. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Electrical Behaviour of Nanostructured Porous Silicon

“…Mesoporous form (crystallites size around 10100 nm) allows thick and mechanically stable porous layer production. It is known as an electrical semi--insulator even at low porosity [19].…”

RF characterization and isolation properties of mesoporous Si by on-chip coplanar waveguide measurements

“…[7,11] and references therein and recent Ref. [9]), deduce the dielectric constant from electrical measurements performed on a metal/porous Si/Si (metal/insulator/semiconductor: MIS) structure. The frequency range of validity of these measurements is, however, limited.…”

“…The approach used in this work is more appropriate for broadband material characterization than the complex impedance analysis [9,17].…”

“…A promising solution in order to reduce RF losses and still remain in batch processing, is to design and fabricate on-chip inductors on an isolating layer of porous Si grown in a CMOScompatible process on the Si substrate [6][7][8][9]. An important step on which we report in this work is the performance of mesoporous silicon, grown locally on the silicon substrate by electrochemistry, as a compact microplate reducing RF losses.…”

“…Research in this direction was presented in Refs. [6][7][8][9][10]. Compared to the thickness of low-loss oxides currently used in standard CMOS, which have a maximum thickness of about 1 lm, very thick porous Si layers can be fabricated on the silicon substrate without severe stress problems.…”