NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes

Kükner, Halil; Weckx, Pieter; Morrison, Sebastien; Raghavan, Praveen; Kaczer, B.; Catthoor, Francky; Perre, Liesbet Van der; Lauwereins, Rudy; Groeseneken, G.

doi:10.1109/dsd.2014.82

Cited by 8 publications

(9 citation statements)

References 28 publications

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“…The structures led to increasing the performance and yield of the adders [3] and reduced the impact of the NBTI in nanometer designs. In [35], a study on the NBTI induced performance degradation of 32bit adders was presented. The study was only performed on RCA and some parallel adder structures.…”

Section: Related Workmentioning

confidence: 99%

“…Furthermore, the study was performed only for the nominal supply voltage level while the effect of the voltage scaling on the performance of the adders and also the impact of the process variation on the performance of the adders were not considered. The studies performed in [35]- [37] on the effect of the NBTI on the CMOS binary adders have shown the importance of the reliability and performance of the adders in nanometers technologies. None of these works has performed a complete study on the impacts of the aggressive voltage scaling including operating in the near-threshold region on the performance and reliability (i.e., speed, power/energy consumption, reliability under the process variations and aging) of the adders in the nano-scaled technologies.…”

Section: Related Workmentioning

confidence: 99%

“…As mentioned before, temporal variations due to aging impacts on the reliability of the CMOS digital circuits during their lifetimes. One of the major causes of these variations is the negative-bias temperature instability (NBTI) phenomenon which is a key reliability issue in the MOSFET (both bulk and FinFET) technologies [5] [35]. The NBTI induces an increase in the threshold voltage and consequently decreases in the drain current of a pMOS (pFET) device.…”

Section: B Impact Of Nbti Aging On the Delay Degradation Of Addersmentioning

confidence: 99%

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A comparative study on performance and reliability of 32-bit binary adders

et al. 2016

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In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: B Impact Of Nbti Aging On the Delay Degradation Of Addersmentioning

confidence: 99%

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A comparative study on performance and reliability of 32-bit binary adders

et al. 2016

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“…To maintain the reliability of fabricated chips, the amount of delay degradation should be estimated and enough margin to avoid malfunction by delay degradation should be maintained. Delay degradation by aging is known to be circuit and workload dependent [1], [2], [3], but previous evaluations are based on simulations, which use transistor degradation model derived from simple circuit measurements. To the best of our knowledge, delay degradation measurement of real circuit under realistic workload has not been reported yet.…”

Section: Introductionmentioning

confidence: 99%

“…This paper aims to realize real circuit delay measurement with enough accuracy for circuit and workload dependent delay degradation estimation. The amount of delay degradation by aging is reported to be typically several percent range [1], [2], [3]. So less than 1.0% delay measurement error is necessary to measure delay degradation.…”

Section: Introductionmentioning

confidence: 99%

Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator

Shimamura

Ikeda

2020

IPSJ Transactions on System LSI Design Methodology

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With the progress of semiconductor process miniaturization, delay degradation by aging increases and threatens the reliability of fabricated chips. The amount of delay degradation is known to be circuit and workload dependent, but previous evaluations are based on simulations, and delay degradation measurement of real circuit under realistic workload has not been reported yet. This paper proposes real circuit delay measurement method, which achieves enough accuracy to measure circuit and workload dependent delay degradation. In the proposed method, onchip oscillator supplies fine resolution variable frequency clock to internal circuit. Internal circuit execute test pattern to activate critical paths at various frequency and determine the maximum frequency at which correct results can be obtained. The maximum frequency corresponds to the delay of the critical paths activated by the test pattern. Clock multiplication improves delay resolution, and repetitive measurement reduces measurement error caused by time dependent random delay variation. The proposed method has been implemented on a 65 nm low power process test chip. Variable frequency oscillator utilizes only standard cells and is designed with automatic layout flow without any timing tuning. The area overhead of the proposed method is 0.09% of the total random logic. The evaluation result show that 0.18% average measurement accuracy has been achieved.

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