Reliability Wearout Mechanisms in Advanced CMOS Technologies 2009
DOI: 10.1002/9780470455265.ch4
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Negative Bias Temperature Instabilities in pMOSFET Devices

A. Strong1,
Ernest Y. Wu2,
R.‐P. Vollertsen3
et al.
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Cited by 7 publications
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References 59 publications
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Voltage stress induced interface states and hole trapping in germanium pMOSFETs with high-k gate dielectric and metal-gate electrode

Chiu
1
,
Chen
2
,
Wu
3
et al. 2021
Materials Science in Semiconductor Processing
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Voltage stress induced interface states and hole trapping in germanium pMOSFETs with high-k gate dielectric and metal-gate electrode

Chiu
1
,
Chen
2
,
Wu
3
et al. 2021
Materials Science in Semiconductor Processing
1
0
0
0
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Observations of negative bias temperature instability defect generation via on the fly electron spin resonance

Ryan
1
,
Lenahan
2
,
Grasser
3
et al. 2010
Applied Physics Letters
47
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17
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An analog perspective on device reliability in 32nm high-κ metal gate technology

Chouard
1
,
More
2
,
Fulde
3
et al. 2011
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
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