Negative Bias Temperature Instability Dependence on Dielectric Thickness and Nitrogen Concentration in Ultra-scaled HfSiON Dielectric/TiN Gate Stacks

Abstract

Negative bias temperature instability (NBTI) of the HfSiON/TiN gate stack is investigated as a function of the dielectric thickness. It is shown that as the thickness of the HfSiON layer is reduced below 20 Å , the NBTI mechanism approaches the mechanism that induces H-reaction diffusion. Conversely, for thicker HfSiON dielectrics, a combination of H-reactiondiffusion and charge detrapping from the bulk HfSiON contribute to NBTI. MOS devives with plasma nitrided HfSiON (30 Å) with varying nitrogen (N) content as gate dielectric are studied with respect to NBTI and it is found that NBTI is dominated by electron detrapping from the bulk and the threshold voltage (V TH) shift reduces monotonically with increasing N content.

Performance Improvement of CoTiO[sub 3] High-k Dielectrics with Nitrogen Incorporation

“…The second approach to avoid the damage from ion implantation was generally to use the N 2 plasma treatments [34][35][36] or postdeposition annealing ͑PDA͒ in nitrogen ambient, such as N 2 , NO, N 2 O, or HH 3 . 37,38 In this work, we use N 2 O plasma treatment ͑at…”

“…The second approach to avoid the damage from ion implantation was generally to use the N 2 plasma treatments [34][35][36] or postdeposition annealing ͑PDA͒ in nitrogen ambient, such as N 2 , NO, N 2 O, or HH 3 . 37,38 In this work, we use N 2 O plasma treatment ͑at bulk and also introduce nitrogen ͑radical of nitrogen in N 2 O plasma͒ in the bulk. Figure 7 shows the SIMS profile for samples with N 2 O plasma treatment ͑20 W͒.…”

Anomalous drain voltage dependence in bias temperature instability measurements on high-κ field effect transistors

“…A detailed description of the gate dielectric manufacturing process is provided in Ref. [4]. Devices with gate lengths of 1.0 lm and 0.7 lm, both with 0.5 lm gate widths, were measured; the two gate length sets gave similar results.…”

Dependency of electrical performances and reliability of 28 nm logic transistor on gate oxide interface treatment methods

“…It was reported that HKMG devices have n ∼ 0.16 and this value could be obtained when both interface trap generation at the IL and charge detrapping at the HK layer took place simultaneously. 21) lifetime than SC-1. Therefore, employing O 3 cleaning in forming the IL/HK interface effectively suppresses the NBTI effect by reducing the initial traps.…”

“…Firstly, energetic holes break the Si-H bonds at the Si/SiO 2 interface, 19,20) and secondly, initial negative fixed charges in the HK layers are detrapped. 21,22) These results indicate that it is crucial to minimize the interface and initial traps when fabricating HK embedded devices. 23,24) Although lots of researches have been focused on the improvement of the IL/HK interface characteristics, the effects of precleaning process in advance to HK deposition has not been studied.…”