Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

Nayak, Kaushik; Bajaj, Mohit; Konar, Aniruddha; Oldiges, P.; Murali, K. V. R. M.; Rao, V. Ramgopal

doi:10.7567/jjap.53.04ec16

Cited by 12 publications

(3 citation statements)

References 39 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The inversion electron density across the channel region reveals that the peak electron charge density of the bulkand SOI FinFET are 1 × 10 19 cm −3 and 8 × 10 19 cm −3 , respectively. This peak value of the charge centroid is situated at the middle of the fin because strong 2D quantum confinement along the fin width causes volume inversion [25]. Figure 3 shows the contour plots of LVT baseline Fin-FET (figure 3…”

Section: Resultsmentioning

confidence: 99%

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Jaisawal

Rathore

Kondekar

et al. 2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/RF and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated TCAD models, to mitigate the leakage current, we analyzed the following approach to get HVT: 1) increasing channel doping (Nch′); 2) making drain-side underlap (Ldsu); 3) increasing gate length (Lg′). Two flavors of FinFETs viz Bulk and SOI (silicon-on-insulator) are suitably compared over their baseline counterpart, i.e., without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of Bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.

show abstract

Section: Resultsmentioning

confidence: 99%

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Jaisawal

Rathore

Kondekar

et al. 2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…The Si GAA NWFET device design and optimization are carried out by following the Si NWFET experimental data reported in [3]. The device simulation parameters for both Si GAA n-and p-NWFETs, in the framework of room temperature drift-diffusion (DD) transport with 2-D carrier confinement and quantum corrections for inversion charge, are calibrated with the experimental data [3] and have been reported in [14] and [15]. In our simulations, the 2-D carrier confinement in the Si GAA NWFET inversion layer is treated via the employed quantum correction model [15], [16] in the room temperature DD numerical simulation framework.…”

Section: -D Device Simulation Results and Discussionmentioning

confidence: 99%

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

Nayak

Agarwal²,

Bajaj³

et al. 2014

IEEE Trans. Electron Devices

Self Cite

View full text Add to dashboard Cite

The metal-gate granularity-induced threshold voltage (V T ) variability and V T mismatch in Si gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The impact of metal-gate crystal grain size on linear and saturation mode V T variability are analyzed. The V T mismatch study predicts lower mismatch figure of merit ( A VT ) in TiN-gated Si GAA n-NWFETs compared with the reported experimental mismatch data for TiN-gated Si FinFETs. Index Terms-Gate-all-around (GAA), metal-gate granularity (MGG), mismatch, silicon nanowire FET, threshold voltage, variability, work function (WF).

show abstract

“…However, due to the geometrically confined structure and low thermal conductivity of the buried oxide (BOX) layer beneath the silicon layer, a self-heating effect (SHE) appears, which is an important and critical challenge for SOI-FinFET devices [3,4]. The SHE deteriorates the carrier velocity and threshold voltage, causing a severe degradation in device performance [5,6].…”

Section: Introductionmentioning

confidence: 99%

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

Banchhor

Chauhan

Bulusu

2021

Semicond. Sci. Technol.

View full text Add to dashboard Cite

The conflicting impacts of temperature on the threshold voltage and mobility, and consequently on the transfer characteristics of a MOSFET, result in a zero-temperature coefficient (ZTC) point. This point is very important for ensuring the stability of the circuit against temperature variations, as the drain current is temperature independent at this bias voltage. In this work, for the first time, we analyze ZTC bias-point instability caused by the self-heating effect (SHE). For this, we discuss the impact of lattice and carrier temperatures, influenced by the SHE, on the ZTC point, which is important in fin field-effect transistors. We report that the SHE causes the ZTC gate bias voltage to be lowered significantly, by about 16% of the overdrive voltage. We also explain the physics of this phenomenon and present a model to explain this change in the ZTC bias caused by the SHE. We discuss the relation between the change in ZTC due to changes in the threshold voltage, saturation velocity, and their temperature derivatives. Our results also show that the drift of the ZTC (i.e. ∆ZTC = ZTC w/oSHE − ZTC withSHE ) is more critical at higher drain-to-source voltages (V DS ). It is important, from an analog-circuit point of view, to predict the ZTC bias point drift caused by the SHE. Furthermore, a common-source amplifier biased at the ZTC predicted by our model-based method is simulated to validate the stability of the circuit against temperature variations. To improve the device design, the device dimensions are optimized to minimize the drift of the ZTC.

show abstract

Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits

Cited by 12 publications

References 39 publications

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

Contact Info

Product

Resources

About