NEMS based thermal management for 3D many-core system

Abstract

Leakage power has become the dominant factor to the total power consumption when technology scales down to nano-region. Moreover, due to the exponential relationship between leakage power and temperature, positive feedback loop can cause thermal-runaway hazard. This poses a significant barrier for 3D integration of multi-cache-core processor, which has high I/O bandwidth but also has high leakage-power density and long heat-removal path. Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices to solve the thermalrunaway problem due to their zero leakage current and infinite subthreshold slope. In order to have a proper control of thermal-runaway hazard for many-core system, this paper studies hybrid CMOS-NEMS designs of thermal buffer and power gating to reduce leakage power and thermal-runaway at thermal-time-constant scale. Experimental results show that our proposed NEMS based thermal management can effectively prevent the thermal-runaway in 3D multi-cache-core processor.

Thermophysical and Geometrical Effects on the Thermal Performance and Optimization of a Three-Dimensional Integrated Circuit

“…Optimization of the power distribution or thermal sources can efficiently improve the thermal profile to avoid overheating. Technological optimization includes low power design [5], rearranging the heat source [6], and so on. Low power design can utilize power switches to control power gate and reduce the leakage power.…”

2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

“…In this thesis, to meet the high-speed, low power and high bandwidth demands, the future thousand-core memory-logic integration by 3D integration is explored. 3D integration by short-distance through-silicon vias (TSV) interconnects [21,22,23,24,25,26,27,28,29,30,31,5,32,33,34,35,36,37,38] and 2.5D integration by middle-distance through-silicon interposer (TSI) interconnects [10,20,39,40,41] can be cost efficient in meeting large bandwidth, low power and latency requirements.…”

“…Thanks to the recent advancement in 3D integration technology [21,22,23,24,25,26,27,28,29,30,31,5,32,33,34,35,36,37,38], which can reduce the physical distance between the memory and the logic blocks, it has shown great potential to integrate thousands of cores with scaled performance superior to that of the 2D integration. 3D in-tegration is identified as key and promising path, not only to facilitate the continuation of the conventional scaling, but also to enable the "more-than-Moore" heterogeneous integration of vast different functionalities into a system in a single chip form.…”