Neuron MOS inverter and source follower using thin-film transistors

Nakamura, Nao; Shimada, Kenji; Matsuda, Tokiyoshi; Kimura, Mutsumi

doi:10.1109/imfedk.2015.7158564

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“…1b is implemented by the weighted synapse portion of Fig. 1a , which is a capacitive voltage adder just like those used in neuMOS devices [8,10]. We can write The inputs in each case is swept from −0.4V to +0.4V in 1 µs.…”

Section: Building Blockmentioning

confidence: 99%

Voltage-Driven Building Block for Hardware Belief Networks

Hassan

Datta

2019

IEEE Des. Test

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Probabilistic spin logic (PSL) based on networks of binary stochastic neurons (or p-bits) has been shown to provide a viable framework for many functionalities including Ising computing, Bayesian inference, invertible Boolean logic and image recognition. This paper presents a hardware building block for the PSL architecture, consisting of an embedded MTJ and a capacitive voltage adder of the type used in neuMOS. We use SPICE simulations to show how identical copies of these building blocks (or weighted p-bits) can be interconnected with wires to design and solve a small instance of the NP-complete Subset Sum Problem fully in hardware.

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Section: Building Blockmentioning

confidence: 99%