New algorithms for the placement and routing of macro cells

Swartz, William J.; Sechen, Carl

doi:10.1109/iccad.1990.129918

Cited by 76 publications

(55 citation statements)

References 12 publications

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“…It is not practical to recalculate the longest path for each move attempt so it is necessary to monitor several possible paths. One solution is, as in previous work [14], to have the designer provide a set of paths or critical nets that the placement algorithm would use in path delay minimization. However, in large designs with complicated interconnect delays, it is very difficult for a user to identify these critical paths a priori.…”

Section: Timing Driven Placementmentioning

confidence: 99%

A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement

Chandy

Banerjee

1999

Journal of Parallel and Distributed Computing

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Section: Timing Driven Placementmentioning

confidence: 99%

A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement

Chandy

Banerjee

1999

Journal of Parallel and Distributed Computing

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“…In this implementation the modified Lam-Delosme schedule is used [9] with rules selected based on quality metrics [10] and dynamic constraint weights [11].…”

Section: Simulated Annealingmentioning

confidence: 99%

A Comparison of Semi-deterministic and Stochastic Search Techniques

Connor¹,

Shea²

2000

Evolutionary Design and Manufacture

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Abstract. This paper presents an investigation of two search techniques, tabu search (TS) and simulated annealing (SA), to assess their relative merits when applied to engineering design optimisation. Design optimisation problems are generally characterised as having multi-modal search spaces and discontinuities making global optimisation techniques beneficial. Both techniques claim to be capable of locating globally optimum solutions on a range of problems but this capability is derived from different underlying philosophies. While tabu search uses a semideterministic approach to escape local optima, simulated annealing uses a complete stochastic approach. The performance of each technique is investigated using a structural optimisation problem. These performances are then compared to each other as and to a steepest descent (SD) method.

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“…Previous timing driven placement schemes have either been net-based [ [18]. Net-based algorithms seek to control the delay on a signal path by putting a separate constraint on each net in the signal path.…”

Section: Introductionmentioning

confidence: 99%

Timing Driven Placement for Large Standard Cell Circuits

Swartz¹

1995

32nd Design Automation Conference

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We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of the art. Our timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. A novel pinpair algorithm controls the delay without the need for user path specification. The timing algorithm is generally applicable to hierarchical, iterative placement methods. Using this algorithm, we present results for the only MCNC standard cell benchmark circuits (fract, struct, and avq.small) for which timing information is available. We decreased the delay of the longest path of circuit fract by 36% at an area cost of only 2.5%. For circuit struct, the delay of the longest path was decreased by 50% at an area cost of 6%. Finally, for the large (22,000 cell) circuit avq.small, the longest path delay was decreased by 28% at an area cost of 6% yet only doubling the execution time. This is the first report of timing driven placement results for any MCNC benchmark circuit.

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New algorithms for the placement and routing of macro cells

Cited by 76 publications

References 12 publications

A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement

A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement

A Comparison of Semi-deterministic and Stochastic Search Techniques

Timing Driven Placement for Large Standard Cell Circuits

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