New configuration memory cells for FPGA in nano-scaled CMOS technology

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

“…Fig. 1 shows an SRAM cell which is presented in our previous work [5]. In this SRAM cell for reducing charge sharing [6], same potential nodes (ST and N1 or STB and N2) are separated from each other [5].…”

“…1 shows an SRAM cell which is presented in our previous work [5]. In this SRAM cell for reducing charge sharing [6], same potential nodes (ST and N1 or STB and N2) are separated from each other [5]. Table 1 lists the sizes of transistors and threshold voltage level in reduced-charge-sharing SRAM cell (RCS-SRAM cell) presented in our previous work [5].…”

“…In this SRAM cell for reducing charge sharing [6], same potential nodes (ST and N1 or STB and N2) are separated from each other [5]. Table 1 lists the sizes of transistors and threshold voltage level in reduced-charge-sharing SRAM cell (RCS-SRAM cell) presented in our previous work [5]. As shown in [5], RCS SRAM cell is completely hardened and cannot flip from particle strikes at the sensitive cell nodes.…”

“…Table 1 lists the sizes of transistors and threshold voltage level in reduced-charge-sharing SRAM cell (RCS-SRAM cell) presented in our previous work [5]. As shown in [5], RCS SRAM cell is completely hardened and cannot flip from particle strikes at the sensitive cell nodes. This SRAM cell can be used as configuration memory cell in configurable FPGA resources [5] and the desired data can be written into cell by using differential write port (WBL and WBLB in Fig.…”

“…As shown in [5], RCS SRAM cell is completely hardened and cannot flip from particle strikes at the sensitive cell nodes. This SRAM cell can be used as configuration memory cell in configurable FPGA resources [5] and the desired data can be written into cell by using differential write port (WBL and WBLB in Fig. 1).…”