New Experimental Findings on Stress Induced Leakage Current of Ultra Thin Silicon Dioxides

Okada, Kenji; Kawasaki, Satoko; Hirofuji, Yuichi

doi:10.7567/ssdm.1994.a-5-5

Cited by 37 publications

(24 citation statements)

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“…The so-called "soft" breakdown (SBD) or "quasi-breakdown" was first reported [160]- [162] in 3-4-nm oxides subjected to either constant-current [161], [162] or constant-voltage [160] stress. After first showing a uniform degradation in the form of SILC, the oxides exhibited a sudden jump to a fluctuating (noisy) current with high leakage at low voltage.…”

Section: A Soft Breakdownmentioning

confidence: 99%

“…The soft breakdown is a localized spot, which can be shown by measuring the area dependence [153], [158], [160], [161], [181] or by viewing the optical emission [17], [161], [181], [183]. The size of this spot is to cm [158].…”

Section: A Soft Breakdownmentioning

confidence: 99%

“…The size of this spot is to cm [158]. Several soft breakdown events, occurring in different spots, may sometimes be seen in large-area devices prior to a hard breakdown [153], [155], [158], [160], [175], [184]. In addition, the SBD current voltage (I-V) characteristic is independent of the oxide thickness at least down to 3 nm, within a band of observed curves [153], [155], [158], [185].…”

Section: A Soft Breakdownmentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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Abstract-The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 nm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO 2 -based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1% of these paths ultimately lead to destructive breakdown, and the microscopic nature of these defects is not known. The rate of defect generation decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron-induced hydrogen release. However, the tunnel current also increases exponentially with decreasing oxide thickness, leading to a decreasing time-to-breakdown and a diminishing margin for reliability as device dimensions are scaled. Estimating the reliability of the dielectric requires an extrapolation from the measurement conditions (e.g., higher voltage) to operation conditions. Because of the diminished reliability margin, it has become imperative to try to reduce the error in this extrapolation.Long-term ( 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin ( 2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown. Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

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Section: A Soft Breakdownmentioning

confidence: 99%

Section: A Soft Breakdownmentioning

confidence: 99%

Section: A Soft Breakdownmentioning

confidence: 99%

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Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Stathis

2001

IEEE Trans. Device Mater. Relib.

163

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“…Experimentally, TDDB is studied by using relatively small-area (compared with typical areas present on circuits) transistor or capacitor test structures [9]. Breakdown events are characterized as "hard" if a short is produced or "soft" if the leakage current increase is limited so that transistor operation can be preserved [10][11][12][13][14]. Frequently, as shown in Figure 7.4, soft breakdown is observed initially leading to an eventual hard breakdown as the stress is continued.…”

Section: Time-dependent Dielectric Breakdown Of Gate Dielectricsmentioning

confidence: 99%

Reliability of silicon integrated circuits

Oates

2015

Reliability Characterisation of Electrical and Electronic Systems

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“…It has been invoked as a possible reason for stress-induced leakage currents [2][3][4][5][6] through elastic [7][8][9][10][11] as well as inelastic [12][13][14][15][16] channels. In thin oxides, the origin of soft breakdown phenomena [17][18][19][20][21][22] is also believed to be related to localized defects.…”

Section: Introductionmentioning

confidence: 99%

Influence of defects on elastic gate tunneling currents through ultrathin SiO2gate oxides: predictions from microscopic models

Städele

Fischer

Tuttle

et al. 2000

Superlattices and Microstructures

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New Experimental Findings on Stress Induced Leakage Current of Ultra Thin Silicon Dioxides

Cited by 37 publications

References 0 publications

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

Reliability of silicon integrated circuits

Influence of defects on elastic gate tunneling currents through ultrathin SiO2gate oxides: predictions from microscopic models

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