New guideline of Vdd and Vth scaling for 65nm technology and beyond

Morifuji, E.; Yoshida, Takeshi; Tsuno, H.; Kimura, Yu; Matsuda, Shôichi; Yamada, Shigeru; Noguchi, T.; Kakumu, M.

doi:10.1109/vlsit.2004.1345457

Cited by 13 publications

(7 citation statements)

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“…In such a circuit, reducing the operating voltage V DD according to the scaling law is difficult because the threshold voltage V th of a transistor can not be decreased because of the leakage current and V th variation. Therefore, V DD should be kept at 1 V [3] or more for logic operation. In this case, the electric field in the scaled-down transistor increases and, as a result, the abrupt source-drain current I ds increases.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Nakata

2006

IEICE Electron. Express

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Abstract:The simplified adiabatic SRAM is proposed which enables gradual charging during writing mode so that problems of electromigration and hot carrier effects can be resolved. For simplicity, we do not use a regenerator circuit for charge recycling in the circuit. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that we set the memory cell power line to be in a high-impedance state. Then, we input adiabatic signal from one bit line to charge the memory cell power line to V DD . This writing method enables gradual discharging and charging. As for reading, the word line voltage is decreased to V th , or it is changed stepwise while the voltages of bit lines are verified. These reading methods enable the gradual change. With the gradual charge transfer in writing and reading modes, the SRAM can avoid electromigration and hot-carrier effects even in the less-than-45-nm process, while it maintains an operating voltage of 1 V or more. Keywords: adiabatic charging, high reliability, SRAM, nanocircuit Classification: Integrated circuits References[1] S. Nakata, "Observation of Coulomb-blockade oscillations by the back gate with subattofarad mutual capacitance," Phys.

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Section: Introductionmentioning

confidence: 99%

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Nakata

2006

IEICE Electron. Express

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“…4. The most part of the charges is transferred to (or from) C L , during transitions, when the active transistors (either M seP and M tsP or M seN and M tsN ) operate in the saturation regime [21,22].…”

Section: Analysis Conditionsmentioning

confidence: 99%

“…This way, every fabrication process is covered. Finally, the current is defined for a gate voltage equals to V DD [22,30]. Then, τ Dm , the delay introduced by a SE inverter, previously defined in (8), becomes:…”

Section: Design Guidelinesmentioning

confidence: 99%

A comprehensive in-depth study of tri-state inverter based DCO

Terosiet

Zianbetov²,

Vallette

et al. 2020

Microelectronics Journal

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“…Read Static Noise Margin (SNM) strongly depends on chip's supply voltage [2]. Thus scaling the supply voltages in different applications such as subthreshold SRAMs and low operating voltage circuits may cause failure in chip performance [2].…”

Section: Introductionmentioning

confidence: 99%

A comparison study of the effects of supply voltage and temperature on the stability and performance of CNFET and nanoscale Si-MOSFET SRAMs

Moradinasab

Karbassian

2009

2009 1st Asia Symposium on Quality Electronic Design

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In this paper we investigate the effects of supply voltage and the temperature on the characteristics of the Static Random Access Memory (SRAM). Two nanoscale SRAM cells based on Carbon Nanotube Field Effect Transistors (CNFETs) and Silicon MOSFET Transistors (Si-MOSFETs) were investigated for application in 32nm technology node. Simulation studies show that the stability of CNFET SRAM against supply voltage variation and temperature influences is larger than those of its Si-MOSFET SRAM counterpart. Furthermore, the circuit performance affected by these two parameters in a 32k SRAM array was investigated. The results show that the read access time in CNFET SRAM arrays based on chirality vectors bigger than (23,0), is less than conventional MOSFET SRAM array. KeywordsCarbon nanotube field-effect transistor (CNFET), SRAM, supply voltage effects, temperature effects.

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New guideline of Vdd and Vth scaling for 65nm technology and beyond

Cited by 13 publications

References 0 publications

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

Adiabatic SRAM with the large margin of Vth variation by the gradual change of the voltage

A comprehensive in-depth study of tri-state inverter based DCO

A comparison study of the effects of supply voltage and temperature on the stability and performance of CNFET and nanoscale Si-MOSFET SRAMs

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