2013
DOI: 10.23919/saiee.2013.8531846
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New Implementation of RSFQ Superconductive Digital Gates

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Cited by 3 publications
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“…The location of the splitters and the length of the interconnects determine the clock skew and delay of each clock path. JTLs are often used within each block if the distance between cells is short [49,61,62].…”
Section: Clock Tree Synthesis In Sfq Systemsmentioning
confidence: 99%