New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress

Hsieh, E. R.; Chung, Steve S.; Tsai, Cheng‐Hung; Huang, Ru; Tsai, C. T.; Liang, C. W.

doi:10.1109/irps.2011.5784610

Cited by 12 publications

(5 citation statements)

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“…These results indicate that scaling strongly worsens ITF. Similar trends of increased trap-induced variability due to higher trapped charge were found also for Si MG-MOSFETs [14], [17], [18]. However, conversely to InGaAs, in Si devices the increased NTRAP was attributed to the effects of aging [14], [18] rather than to Fig.…”

Section: Variability Analysissupporting

confidence: 77%

“…Moreover, it allows determining the impact of randomized interface-trap concentration on the total variability providing insights into the limitations of InGaAstechnology scaling. The variability due to random interfacetrap density (DIT), trap number, and location was evaluated for Si Multi-Gate (MG) MOSFETs finding that its impact increases due to the generation of defects as a consequence of aging [14], [17], [18]. As InGaAs MOSFETs exhibit higher native DIT (i.e., even before degradation due to aging) compared to Si [19], here we focus on the variability to assess due to native interface traps.…”

Section: Introductionmentioning

confidence: 99%

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Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Zagni

Caruso

Puglisi

et al. 2020

IEEE Trans. Electron Devices

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Thanks to their superior transport properties, Indium Gallium Arsenide (InGaAs) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) constitute an alternative to conventional Silicon MOSFETs for digital applications at ultrascaled nodes. The successful integration of this technology is challenged mainly by the high defect density in the gate oxide and at the interface with the semiconductor channel, which degrades the electrostatics and could limit the potential benefits over Si. In this work, we i) establish a systematic modeling approach to evaluate the performance degradation due to interface traps in terms of electrostatics and transport of InGaAs Dual-Gate Ultra-Thin Body (DG-UTB) FETs, and ii) investigate the effects of random interface-trap concentration as another roadblock to the scaling of the technology, due to statistical variability of the threshold voltage. Variability is assessed with a Technology CAD (TCAD) simulator calibrated against Multi-Subband Monte Carlo (MSMC) simulations. The modeling approach overcomes the TCAD limitations when dealing with ultra-thin channels (i.e., below 5 nm) without altering crucial geometrical parameters that would compromise the dependability of the variability analysis. Our results indicate that interface-trap fluctuation becomes comparable with the other variability sources dominating the total variability when shrinking the device dimensions, thus contrasting the trend of reduced variability with scaling. This in turn implies that interface and border traps may strongly limit the benefits of InGaAs over Silicon if not effectively reduced by gate process optimization.

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Section: Variability Analysissupporting

confidence: 77%

Section: Introductionmentioning

confidence: 99%

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Zagni

Caruso

Puglisi

et al. 2020

IEEE Trans. Electron Devices

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“…Since HCD is driven by the interaction of hot and cold carriers [4,10,11] and is thus determined by the carrier energy distribution function (DF), degradation proceeds with different rates in various samples. This issue has been addressed experimentally [12][13][14][15] and in simulation approaches [16][17][18][19] by different groups. However, all previous simulation approaches only provide a statistical description of HCD based on some phenomenological models which do not reveal the complex physical picture behind HCD which includes also the impact of RDs.…”

Section: Introductionmentioning

confidence: 99%

Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs

Makarov

Kaczer

Roussel

et al. 2019

IEEE Electron Device Lett.

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Using the deterministic version of our hot-carrier degradation (HCD) model we perform a statistical analysis of the impact of random dopants (RDs) on HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

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“…Among reliability issues, hot-carrier degradation (HCD) has repeatedly been reported [10,11] to be the most detrimental one. Nevertheless, there is a very limited number of papers presenting experimental investigations of variability induced by HCD [9,[12][13][14]. The few modeling approaches to HCD variability are limited to phenomenological descriptions and do not address the complex physical picture of HCD [15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

Makarov

Kaczer

Chasin

et al. 2019

IEEE Electron Device Lett.

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We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hotcarrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration Nit. These deterministic densities Nit for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

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New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress

Cited by 12 publications

References 0 publications

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs

Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs

Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach

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