New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA

Delorme, Julien; Nafkha, Amor; Leray, Pierre; Moy, Christophe

doi:10.1109/reconfig.2009.69

Cited by 18 publications

(13 citation statements)

References 7 publications

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“…There have been already works which used burst transfer to speed up reconfiguration [12], [13]. When compared to them, this work proposes a novel architecture of the controller which not only accelerates reconfigurations but also readbacks and additionally handles the physical aspects of the reconfiguration and preemption.…”

Section: Framework Overviewmentioning

confidence: 99%

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Jozwik

Tomiyama

Honda

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYModern FPGAs (Field Programmable Gate Arrays), such as Xilinx Virtex-4, have the capability of changing their contents dynamically and partially, allowing implementation of such concepts as a HW (hardware) task. Similarly to its software counterpart, the HW task shares time-multiplexed resources with other HW tasks. To support preemptive multitasking in such systems, additional context saving and restoring mechanisms must be built practically from scratch. This paper presents an efficient method for hardware task preemption which is suitable for tasks containing both Flip-Flops and memory elements. Our solution consists of an offline tool for analyzing and manipulating bitstreams, used at the design time, as well as an embedded system framework. The framework contains a DMA-based (Direct Memory Access), instruction-driven reconfiguration/readback controller and a developed lightweight bus facilitating management of HW tasks. The whole system has been implemented on top of the Xilinx Virtex-4 FPGA and showed promising results for a variety of HW tasks.

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Section: Framework Overviewmentioning

confidence: 99%

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Jozwik

Tomiyama

Honda

et al. 2012

IEICE Trans. Inf. & Syst.

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“…The tests conducted show a throughput that ranges from 2.99 to 3.14 Gbps. In [54], the authors propose a reconfiguration controller based on three components: an external SRAM memory exclusively dedicated to store the partial bitstreams, a custom reconfiguration controller with access to the ICAP interface, and a MicroBlaze processor interfaced via the CoreConnect OPB bus to the reconfiguration controller through several configuration registers. The reconfiguration controller, after receiving the configuration commands from MicroBlaze, performs the reconfiguration process autonomously.…”

Section: Recent Advances In the Design And Development Of Reconfiguramentioning

confidence: 99%

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

Fons

Cantó

et al. 2011

J Sign Process Syst

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Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time-through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources-and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.

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“…The theoretical maximum throughput of the ICAP interface that is used to access the internal configuration memory of the Virtex 4 FPGA is 400 MB/s [57]. A custom intellectual property (IP) capable of achieving the theoretically maximum partial reconfiguration throughput through the ICAP interface was recently reported [16]. The above IP uses a processor only for initialization and performs the subsequent transfer of configuration data autonomously.…”

Section: Fine-grained Reconfigurable Fabric With Lookup Table Based Cmentioning

confidence: 99%

Flexibility and Reusability in the Digital Front-End of Cognitive Radio Terminals

Michael

Vinod

Moy

et al. 2011

Circuits Syst Signal Process

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From the issue entitled "Special Issue on Embedded Signal Processing Circuits and Systems for Cognitive Radio-Based Wireless Communication Devices"International audienceEmerging communication paradigms like the cognitive radio require extremely flexible physical layer functional units that can be parameterized at runtime for supporting multiple modes. Parameterizing the hardware accelerators in the cognitive radio baseband incurs a latency penalty, which is a function of the amount of reconfiguration data required by the accelerators. In an opportunistic spectrum access scenario, the cumulative latency required to reconfigure all the physical layer units when switching to a new channel, reduces the useful time available for transmission leading to a lower system throughput. Against this background, this paper gives an overview of the amount of reconfiguration data required by different candidate accelerator architectures for performing the computationally intensive channelization function, in the digital front-end of the cognitive radio terminal. The paper also identifies opportunities for reusing hardwired stages of a channelization accelerator across multiple modes, while minimizing the reconfiguration overhead

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New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA

Cited by 18 publications

References 7 publications

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

Flexibility and Reusability in the Digital Front-End of Cognitive Radio Terminals

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