New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Abstract

We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure f r om previous approaches in that we derive an explicit area/delay tradeo curve. We achieve this goal by limiting the solution space to the set of topologies induced b y a p ermutation on the sinks of the net. This constraint allows ecient identication of optimal solutions while still providing a rich solution space. We also incorporate simultaneous wire sizing. Our technique consistently p r o duces topologies equalling the performance o f previous approaches with substantially less area overhead.

Concurrent flip-flop and repeater insertion for high performance integrated circuits

“…To this purpose we have incorporated our repeater insertion strategy and the P-Tree AT [3] routing tree construction technique in two new algorithms referred here as to FloP-Tree-ML and FloP-Tree-GL based on the MiLa and GiLa algorithms, respectively. Aside from testing the correctness of the proposed methodology this has also served us in verifying that our technique is indeed amenable to being employed in other interconnect design algorithms based on the same dynamic programming style of [1] to extend them to the broader case of clocked repeater insertion.…”

“…Section 3 of the MiLa algorithm computes the optimal covers of subtree θ u when its root is connected to two branches b u,v and b u,z . A methodology for joining covers without taking into account latency was given in [1] and more formally in [3]. The same method, extended to the latency case, is implemented in the function merge outlined in Figure 9.…”

“…An elegant dynamic programming algorithm was proposed in [1] to determine optimal repeater assignments of the candidate locations of a given interconnect topology. Several other works based on the same technique, [3][4][5][6][7] to cite a few, have also been proposed incorporating other optimization steps such as noise or area minimization, wire sizing, etc. All of these works, however, only consider the case where a signal is required to arrive at its destination within one single clock cycle.…”

Leveraging delay slack in flip-flop and buffer insertion for power reduction

“…Routing techniques have been studied in [4] for congestion minimization, in [8,5] for performance optimization, and in [7,13] for crosstalk minimization. However, all of these algorithms run directly on a flat routing models, and may suffer the scalability problems for large designs.…”

An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations

“…Topology search based algorithms P-Tree [1], S-Tree [2], and SP-Tree [3] limit the routing topology space to certain topologies and search exhaustively for the best solution in that limited space. The final routing tree obtained from these algorithms depends on the criteria used to limit the topology space and the initial routing topology given to these algorithms.…”