Concurrent flip-flop and repeater insertion for high performance integrated circuits

Cocchini, P.

doi:10.1109/iccad.2002.1167545

Cited by 20 publications

(17 citation statements)

References 10 publications

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“…Inserting pipeline registers to long wires would improve performance [3,7,13,14]. Earlier work [5] proposed to use a pipeline primitive to cut long wires in shorter segments.…”

Section: Pipeline Insertionmentioning

confidence: 99%

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Dukkipati

Gibb

McKeown³

et al. 2007

15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)

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A Mesh of Trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing [5]. In this paper, we report our findings in bringing this concept to silicon. Specifically, we conduct cycle-accurate verilog simulations to verify the analytical results claimed in [5]. We synthesize and obtain the layout of the MoT interconnection networks of various sizes. To further improve throughput, we investigate different arbitration primitives to handle load and store, the two most common memory operations. We also study the use of pipeline registers in large networks when there are long wires. Simulation based on full network layout demonstrates that significant throughput improvement can be achieved over the original proposed MoT interconnection network. The importance of this work lies in its validation of performance features of the MoT interconnection network, as they were previously shown to be competitive with traditional network solutions. The MoT network is currently used in an eXplicit Multi-Threading (XMT) on-chip parallel processor, which is engineered to support parallel programming. In that context, a 32-terminal MoT network could support up to 512 on-chip XMT processors. Our 8-terminal network that could serve 8 processor clusters (or 128 total processors), was also accepted recently for fabrication.

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“…Inserting pipeline registers to long wires would improve performance [3,7,13,14]. Earlier work [5] proposed to use a pipeline primitive to cut long wires in shorter segments.…”

Section: Pipeline Insertionmentioning

confidence: 99%

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Dukkipati

Gibb

McKeown³

et al. 2007

15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)

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“…Even with the repeater insertion the delay in the wires can exceed one clock period and multiple clock periods will be needed to transfer the data. There has been some work done to optimally insert latches in the wire to improve the throughput [8,10].…”

Section: Figure 1: An Abstraction Of a Communication Link In An Nocmentioning

confidence: 99%

A low power approach to system level pipelined interconnect design

Chandra

Schmit

2004

Proceedings of the 2004 International Workshop on System Level Interconnect Prediction

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System on Chip interconnects require first-in first-out buffers (FIFOs) to handle different data rates between IP cores. The design of an interconnect channel containing multiple stages of FIFO require making tradeoff between throughput and power consumption. The design variables are the sizes of the FIFOs, their voltages and their clock frequencies. Decreasing the FIFO clock frequencies saves power but it causes the channel performance (throughput) to decrease. In this work, we recover the performance by resizing the FI-FOs in the channel. The voltage and clock scaling in the interconnect channel followed by FIFO resizing approach leads to significant power savings. The power savings is a function of system parameters λ (expected data production rate) and µ (expected data consumption rate). We observed a maximum dynamic power savings of 45.8%, 28.9% and 11.3% for min(λ, µ) of 0.2, 0.5 and 0.8 respectively. Our approach of reducing voltage in the interconnect channel will reduce the leakage power as well.

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“…The primary methodological impact is in the dynamic management of the physical design hierarchy that must now manage netlists that change on the fly due to repeaters, as well as handle repeaters from other levels of the hierarchy. Another major problem arises because of the increasing instances of pipelined interconnects [9]. A small error in the early prediction of the sequential latency of an interconnect can lock the logic at its sink into a sub-optimal or infeasible pipeline stage, whereas retiming some logic at a late phase can invalidate early architectural performance simulations, dynamic validation suites, formal verification proofs and RTL accuracy (due to back-annotation issues) under many current methodologies.…”

Section: Impact On Post-rtl Cadmentioning

confidence: 99%

The scaling challenge

Saxena

Menezes

Cocchini

et al. 2003

Proceedings of the 2003 International Symposium on Physical Design

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We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of correctby-construction (CbC) design. We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. Finally, we suggest CbC approaches to tackle the new synthesis and layout challenges identified in this paper.

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Concurrent flip-flop and repeater insertion for high performance integrated circuits

Cited by 20 publications

References 10 publications

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

A low power approach to system level pipelined interconnect design

The scaling challenge

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