New Super-Junction LDMOS Based on Poly-Si Thin-Film Transistors

Tsai, Jhen-Yu; Hu, Hsin‐Hui

doi:10.1109/jeds.2016.2600253

Cited by 4 publications

(1 citation statement)

References 25 publications

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“…[1][2][3] Lateral double-diffused metal-oxidesemiconductor field-effect transistor (LDMOS) is a key device for the PIC, but it is not area efficient and suffers the contradiction between the BV and specific on-resistance R on,sp . The BV of the power device is limited by the low lateral BV for the poor surface electric field distribution, and some work has been carried out, such as the variable lateral doping (VLD), [4][5][6][7] super junction, [8,9] and charge islands. [10] Enhancing the electric field (ENDIF) of the dielectric buried layer is a feasible method to increase the vertical BV and several new structures have been developed [11][12][13][14][15] in which introducing self-adaptive interface charges are effective and attractive.…”

Section: Introductionmentioning

confidence: 99%

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Li¹,

Zhang²,

Li³

et al. 2019

Chinese Phys. B

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A stacked lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (R on,sp ). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The R on,sp decreases from 39.62 mΩ•cm 2 to 23.24 mΩ•cm 2 and the Baliga's figure of merit (FOM) of is 9.07 MW/cm 2 .

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Section: Introductionmentioning

confidence: 99%

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Li¹,

Zhang²,

Li³

et al. 2019

Chinese Phys. B

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Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

Zhu

Jia

Yang

2022

Silicon

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ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side

Chen

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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This paper studies a composite power n-channel lateral-diffused MOSFET device with a super junction (SJ) and parasitic silicon-controlled rectifier structure (nLDMOS-SJ-SCR) in the drain side, which can be used for electrostatic discharge (ESD) and latch-up (LU) reliability enhancements of 60-V power electronics. For ESD and LU protection considerations, the drain side with an SJ structure integrated with p-n-p-and n-p-n-arranged types of nLDMOS-SCR transistors is demonstrated. According to the experimental data, the layout of the SJ structure in the drain side has positive effects on ESD and LU capabilities. The layout type of nLDMOS-SJ with a pillar width W= 9 μm has the highest secondary breakdown current (It2) values; the ESD (LU) improvement was 46.3% (13.3%) compared with the nLDMOS reference sample. Meanwhile, an nLDMOS-SJ with a pillar width W= 27 μm has the highest figure of merit (FOM) value. By contrast, an embedded p-n-p-(n-p-n-)arranged type SCR structure was added into the drain side once again. Initially, it has a positive (negative) effect on the ESD reliability. Furthermore, the ESD (figure of merit; FOM) improvement was 37.9% (13.72%) of the corresponding nLDMOS-SJ device for nLDMOS-SJ-SCR (p-n-p) with W= 27 μm. Overall, an nLDMOS-SJ device integrated with the p-n-p-arranged-type SCR in the drain side is a favorable choice for ESD and LU improvements.

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New Super-Junction LDMOS Based on Poly-Si Thin-Film Transistors

Cited by 4 publications

References 25 publications

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side

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