Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Li, Qi; Zhang, Zhaoyang; Li, Haiou; Sun, Tangyou; Chen, Yonghe; Yuan, Zhen-Sheng

doi:10.1088/1674-1056/28/3/037201

Cited by 3 publications

(2 citation statements)

References 23 publications

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“…At present, the field plate commonly used in the IC (Integrated circuit) manufacturing industry are two structures: mini-STI (Shallow trench isolation) field plate and mini-LOCOS (Local oxidation of silicon) field plate [6] [7]. Many new researchers have been published [8] [9][10] [11] [12], and they focus on optimizing and innovating field plate structures in LDMOS devices. These novel field plate structures indeed bring a significant improvement in device FOM (Figures of merits) performance to a certain degree.…”

Section: Introductionmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low , (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length L, field plate thickness H, and slot contact width W, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that , can achieve as low as 6.9m•mm 2 when the source-drain (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W=10 m) and very large devices (W= 2mm). Index Terms-Contact field plate (CFP), Figures of merits (FOM), Lateral double diffusion metal oxide semiconductor (LDMOS), Specific on-resistance ( , )

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Section: Introductionmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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“…Silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor (LDMOS) devices are applicable to high-voltage power integrated circuits for industrial and automotive applications, due to their properties of ideal isolation, high breakdown voltage, low leakage current, and good compatibility. [1][2][3] One of the most important issues in the design of SOI LDMOS devices is to relieve the contradiction between the breakdown voltage (BV) and specific on-resistance R on,sp . To overcome such a contradiction, designs of drift doping profiles have been explored to modulate the electric field of SOI LDMOS devices.…”

Section: Introductionmentioning

confidence: 99%

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Yao¹,

Guo²,

Zhang³

et al. 2020

Chinese Phys. B

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This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (R on, sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R on, sp compared to the SD device and HK device.

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A super-junction SOI-LDMOS with low resistance electron channel

Chen¹,

Huang²,

Huang³

et al. 2021

Chinese Phys. B

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A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance (R on,sp) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage (BV) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R on,sp of the device can reach 253 V and 15.5 mΩ ⋅ cm2, respectively, and the Baliga’s figure of merit (FOM = BV 2/R on,sp) of 4.1 MW/cm2 is achieved, breaking through the silicon limit.

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Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Cited by 3 publications

References 23 publications

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

A super-junction SOI-LDMOS with low resistance electron channel

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