Next Generation FPGAs and SOCs - How Embedded Systems Can Profit

Eberli, Felix

doi:10.1109/cvprw.2013.92

Cited by 7 publications

(3 citation statements)

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“…The platform supports data transmission through the AMBA AXI bus into the FPGA fabric [26]. This allows for efficient and workloadspecific designs of accelerator-enabled servers and mobile systems [9]. Clusters of hybrid ARM-FPGA SoCs using ARM processors as a data transfer controller for distributed FPGA processing such as the ZCluster, are also beginning to emerge and demonstrate superior performance than homogeneous clusters for data-intensive applications by elasticity, e.g.…”

Section: Introductionmentioning

confidence: 99%

Runtime support for adaptive power capping on heterogeneous SoCs

Nikolopoulos

Woods

2016

2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

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Section: Introductionmentioning

confidence: 99%

Runtime support for adaptive power capping on heterogeneous SoCs

Nikolopoulos

Woods

2016

2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

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“…These platforms are well suited for server design exploration, as they have enough processing, storage and memory to run modern server workloads [7]. Whilst power capping methods based on DVFS have been investigated for homogeneous, high-performance compute servers [8] [9], their application on heterogeneous systems and in particular systems based on embedded design methods has been limited [10] [11].…”

Section: Introductionmentioning

confidence: 99%

Power modelling and capping for heterogeneous ARM/FPGA SoCs

Nunez-Yanez

Woods

et al. 2014

2014 International Conference on Field-Programmable Technology (FPT)

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Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of highperformance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

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“…One application of this technology that they believe will have a significant impact is in vision systems. Eberli 13 analyzed some of the applications of FPGA-SoCs and concluded that these will help solve some of the problems associated with embedded systems that could not be solved a few years ago. The proper combination of the high-level programming available in the processors with the pixel-level parallelism of FPGAs can solve one of the main disadvantages of FPGAs, ie, their high software development time, and thus facilitate the development of embedded systems with lower energy consumption and reduced size.…”

mentioning

confidence: 99%

FPGA‐SoC implementation of an ICA‐based background subtraction method

Carrizosa-Corral

Vázquez-Cervantes

Montes

et al. 2018

Circuit Theory & Apps

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SummaryThis paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the architecture of the FPGA‐SoC with embedded processor. This recent technology complements the parallelism of the FPGA with the general‐purpose computing capacity of the processors while maintaining low energy consumption and a compact size. The above features are appropriate for autonomous devices that handle mainly background subtraction, while a central device receives this information and performs the remaining tasks required for the application. The use of processors allows a faster implementation and integration of the device into other systems in a simple manner, while the parallelism of the FPGA increases the processing speed by accelerating intensive numeric calculations. The results obtained from the implementation that uses both FPGA and the embedded processor of the SoC show an increase of 3300% in the number of frames per second compared with an implementation that uses only the embedded processor.

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Next Generation FPGAs and SOCs - How Embedded Systems Can Profit

Cited by 7 publications

References 1 publication

Runtime support for adaptive power capping on heterogeneous SoCs

Runtime support for adaptive power capping on heterogeneous SoCs

Power modelling and capping for heterogeneous ARM/FPGA SoCs

FPGA‐SoC implementation of an ICA‐based background subtraction method

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