NoC Design of a Video Encoder in a Multiprocessor System on Chip Solution

Portero, Antoni; Pla, R.; Rodríguez, Alonso Mateos; Carrabina, Jordi

doi:10.1109/icm.2005.1590067

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…NoC are usually design for a specific application [20]. An example of previous work is an NoC architecture designed for video encoder application [21]. Another previous work is an NoC designed for image and signal processing applications [22].…”

Section: Literature Reviewmentioning

confidence: 99%

UTAR NoC: Adaptive Network on Chip architecture platform

Lokananta

Lee

et al. 2015

2015 3rd International Conference on New Media (CONMEDIA)

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Network-on-Chip (NoC) has been proposed as a solution for the communication challenges of Multi-ProcessorSystem-on-chip (MPSoC) design in nanoscale technologies and it has better reusability and scalability. However along with the advantages of any communication parameter follow its disadvantages. Most state-of-the-art NoC architecture and their design flows is optimized for a single application, and no single NoC can provide optimal performance across a wide range of applications. In this research, a reconfigurable and adaptable Network-on-Chip architecture is proposed. Adaptive routing components are designed to enable the router to select a path with less congestion. Parameterize file is designed to enable the NoC to be reconfigured and scalable.

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Section: Literature Reviewmentioning

confidence: 99%

UTAR NoC: Adaptive Network on Chip architecture platform

Lokananta

Lee

et al. 2015

2015 3rd International Conference on New Media (CONMEDIA)

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“…Some research works focus on the application partitioning and mapping [1,2]. Other researches try to improve the network topology [3] or the routing algorithm [4,5].…”

Section: Introductionmentioning

confidence: 99%

A scalable bootloader and debugger design for an NoC-based multi-processor SoC

Hartono

Lim

et al. 2015

2015 3rd International Conference on New Media (CONMEDIA)

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This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this design approach, the bootloader and debugger require relatively small hardware overhead and are able to fully utilize the benefit of the NoC architecture's scalability.

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Introducing Energy and Area Estimation in HW/SW Design Flow Based on Transaction Level Modeling

Cheema

Hammami

2006

2006 International Conference on Microelectronics

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NoC Design of a Video Encoder in a Multiprocessor System on Chip Solution

Cited by 3 publications

References 11 publications

UTAR NoC: Adaptive Network on Chip architecture platform

UTAR NoC: Adaptive Network on Chip architecture platform

A scalable bootloader and debugger design for an NoC-based multi-processor SoC

Introducing Energy and Area Estimation in HW/SW Design Flow Based on Transaction Level Modeling

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