Noise tolerant low voltage XOR-XNOR for fast arithmetic

El-Gamel, Mohamed; Goel, S.; Bayoumi, Magdy

doi:10.1145/764867.764882

Cited by 7 publications

(14 citation statements)

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“…The results of simulation which included a delay, power dissipation and power delay product are listed in Table 3 and also are represented in Figure 7, 8, 9, 10 and 11. The results indicate that the delay of the proposed XOR-XNOR circuit is smaller than previous circuit in Figure 2[3], [6] and [5], and nearly similar to circuit in Fig 1[3] and [7]. But in terms of power consumption, the proposed circuit consumes less power compared to other design except for the circuit in [6] which consumes less power than other circuits but [6] offer slowest speed at a low voltage.…”

Section: Gatesupporting

confidence: 54%

“…Numerous designs were reported to realize the XOR-XNOR functions using different number of circuit techniques and approaches [1], [2], [3], [4], [5], [6], [7]. They vary in methodologies and transistor count to improve the circuit performance in term of speed and density.…”

Section: Previous Workmentioning

confidence: 99%

“…Elgamel et al [7] proposed an improved version of [6] in Figure 4 and has better power-delay product and higher noise immunity. In [5], the XOR-XNOR circuit adds a forward and backward feedback between the XOR and XNOR gate and additional transistors to rectify the degraded logic level problem.…”

Section: Previous Workmentioning

confidence: 99%

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A new design of XOR-XNOR gates for low power application

Ahmad

Hasan

2011

2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA)

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Abstract-XOR and XNOR gate plays an important role in digital systems including arithmetic and encryption circuits. This paper proposes a combination of XOR-XNOR gate using 6-transistors for low power applications. Comparison between a best existing XOR-XNOR have been done by simulating the proposed and other design using 65nm CMOS technology in Cadence environment. The simulation results demonstrate the delay, power consumption and power-delay product (PDP) at different supply voltages ranging from 0.6V to 1.2V. The results show that the proposed design has lower power dissipation and has a full voltage swing.

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Section: Gatesupporting

confidence: 54%

Section: Previous Workmentioning

confidence: 99%

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A new design of XOR-XNOR gates for low power application

Ahmad

Hasan

2011

2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA)

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“…Some conclusions are shown in Section IV. [21].To amend the circuit performance in terms of speed and density the transistor count and methodologies kept changing in these previous papers. In [16] the conventional design of XOR-XNOR circuit using static CMOS network can be found.…”

Section: Fig 1 3d Structure and Cross-sectional View Of Finfet Devicementioning

confidence: 99%

“…Design in the [21] is an improved version of [20] shown in fig. 5 and has improved power-delay product and higher noise resistance.…”

Section: Previous Workmentioning

confidence: 99%

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

Yadav¹,

Khandelwal²,

Akashe³

2013

IJCA

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As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

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