Non-uniform multilevel analog routing with matching constraints

Ou, Hung-Chih; Chien, Hsing-Chih Chang; Chang, Yao‐Wen

doi:10.1145/2228360.2228458

Cited by 25 publications

(13 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recently, other than symmetry issue, exact matching constraints for maze routing are well addressed in [14]. Ou et al in [15] first define three typical matching constraints for analog routing which dominates performance most: (1)symmetry, (2)topology-matching and (3)length-matching.…”

Section: A Previous Workmentioning

confidence: 99%

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Pan

Chin

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper firstly introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation (CDT). And later this crossing graph can be migrated into multiple layouts with placement and routing reconnection. The proposed approach also provides a refinement for wire to optimize the performance metrics. This approach is applied to a variablegain amplifier (VGA), a folded-cascode operational amplifier (OpAmp) and a low dropout regulator (LDO). The experimental results demonstrate more possibility on layout migration, such that averagely more than 75% routing of migrated layout is generated by our approach. Additionally, it exhibits the productivity with qualified performance on different designs.

show abstract

Section: A Previous Workmentioning

confidence: 99%

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Pan

Chin

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…the total wirelength O w (n k ) of net n k is defined in (1). e) Routing conservation constraint: The routing conservation constraint guarantees that the route of each net is consecutive and nonbranched.…”

Section: B Basic Ilp Formulationmentioning

confidence: 99%

Nonuniform Multilevel Analog Routing With Matching Constraints

Chien²,

Chang

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Symmetry, common-centroid, topology-matching, and length-matching constraints are four major routing considerations to improve the performance of an analog circuit. Symmetry constraints are specified to route matched nets symmetrically with respect to some common axes. Common-centroid constraints are also specified to route matched net symmetrically with respect to some common centers. Topology-matching constraints are commonly imposed on critical yet asymmetry nets with the same number of bends, vias, and wirelength. Length-matching constraints are specified to route the nets which have limited resources with the same wirelength. These four constraints can reduce current mismatches and unwanted electrical effects between two critical nets. In this paper, we propose the first work to simultaneously consider the four constraints for analog routing while minimizing total wirelength, bend numbers, via counts, and coupling noise at the same time. We first present a basic integer linear programming (ILP) formulation to simultaneously consider the four constraints for analog routing. Then, a prioritized-constraint-aware routing algorithm is proposed to assist analog designers for assigning the four matching constraints and optimizing routing topologies. Effective reduction techniques are also employed to reduce the numbers of ILP variables and constraints for the two routing algorithms. To further enhance the routing performance, a nonuniform multilevel routing framework is presented and integrated into our routing algorithms. Experimental results show that our approach can obtain better routing results and satisfy all specified routing constraints while optimizing circuit performance.

show abstract

“…In designing analog and/or digital integrated circuits, it is not uncommon that their layouts contain non-orthogonal (nonManhattan) polygons [10,11]. For example, to decrease the effects of corner etching, the layout of a unit cell capacitor can have 45-degree corners [10].…”

Section: Parameterized 45-degree Polygons With Linear Constraintsmentioning

confidence: 99%

Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids

Tseng

Huang

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

View full text Add to dashboard Cite

In this paper, an approach to the partitioning of parameterized 45-degree polygons into parameterized trapezoids by using horizontal cuts is proposed. In the process of partitioning a parameterized 45-degree polygon, the proposed approach invokes a mixed integer linear programming solver only once and can rapidly obtain results of comparing linear expressions. Compared with previous partitioning programs, the program implementing the proposed approach is very efficient and can achieve more than 100x speed-up while partitioning large parameterized polygons or parameterized polygons with complex constraints. The approach can be used as the basis to build trapezoidal corner stitching data structures for parameterized 45-degree layouts so that models of layout-induced parasitics can be generated automatically.

show abstract

Non-uniform multilevel analog routing with matching constraints

Cited by 25 publications

References 8 publications

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Nonuniform Multilevel Analog Routing With Matching Constraints

Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids

Contact Info

Product

Resources

About