Non-volatile one-transistor-cell multiple-valued CAM with a digit-parallel-access scheme and its applications

Hanyu, Takahiro; Kanagawa, Naoki; Kameyama, Michitaka

doi:10.1016/s0045-7906(97)00027-x

Cited by 7 publications

(7 citation statements)

References 7 publications

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“…CAM architecture is constructed with an array of memory elements along with comparison circuits. Memory elements can either be volatile or nonvolatile [18]. Generally, 6T static random access memory (SRAM) cell is used to build the memory [19].…”

Section: Traditional Cam Architecturementioning

confidence: 99%

Hybrid self-controlled precharge-free CAM design for low power and high performance

Satyanarayana¹,

Sridevi²

2019

Turk J Elec Eng & Comp Sci

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Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V. Simulation results show that the proposed HSCPF CAM-type ML design reduces power consumption and search delay effectively when compared to recent precharge-free CAM-type ML architectural designs.

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Section: Traditional Cam Architecturementioning

confidence: 99%

Hybrid self-controlled precharge-free CAM design for low power and high performance

Satyanarayana¹,

Sridevi²

2019

Turk J Elec Eng & Comp Sci

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“…(d)-(i) TCAM cells based on nonconventional memory technologies. (d)-(g) TCAM cells based on flash memory [48], hybrid CMOS/MRAM [49], CMOS/STT-RAM [50], and CMOS/memristors [51] technologies, respectively. (i) Memristor-based implementation.…”

Section: Background a Pattern Matchingmentioning

confidence: 99%

“…(i) Memristor-based implementation. memory [48], hybrid CMOS/magnetic random access memory (MRAM) [49], CMOS/spin torque transfer (STT)-RAM [50], and CMOS/memristor [51] circuits. In this paper, we consider the implementation of TCAM cell with a pair of two memristors [ Fig.…”

Section: Background a Pattern Matchingmentioning

confidence: 99%

High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

Madhavan

Sherwood

Strukov

2018

IEEE Trans. VLSI Syst.

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In this paper, we propose a novel CMOS+ MOLecular (CMOL) field-programmable gate array (FPGA) circuit architecture to perform massively parallel, high-throughput computations, which is especially useful for pattern matching tasks and multidimensional associative searches. In the new architecture, patterns are stored as resistive states of emerging nonvolatile memory nanodevices, while the analyzed data are streamed via CMOS subsystem. The main improvements over prior work offered by the proposed circuits are increased nanodevice utilization and, as a result, substantially higher throughput, which is demonstrated by a detailed analysis of the implementation of pattern matching task on the new architecture. For example, our estimates show that the proposed CMOL FPGA circuits based on the 22-nm CMOS technology and one crossbar layer with 22-nm nanowire half-pitch allows up to 12.5% average nanodevice utilization, i.e., the fraction of the devices turned to the high conductive state, as compared to a typical ∼0.1% of the original CMOL FPGA circuits. This in turn enables throughput close to 7.1 × 10 16 bits/s/cm 2 at ∼ 1 fJ/bit energy efficiency, for matching of ∼ 10 7 250-bit patterns stored locally on a 1 cm 2 chip. These numbers are at least 2 orders of magnitude better throughput as compared to that of other state-of-the-art FPGA methods, and begin to approach ternary content-addressable memory-like performance at similar CMOS technology nodes. More generally, we argue that the proposed concept combines the versatility of reconfigurable architectures and density of the associative memories. It can be viewed as a very tight symbiotic integration of memory and logic functions for high-performance logic-in-memory computing. Index Terms-CMOS+MOLecular (CMOL), fieldprogrammable gate array (FPGA), hybrid circuits, logicin-memory computing, memristor, pattern matching, ReRAM, resistive switching, ternary content-addressable memory (TCAM). I. INTRODUCTION R ECONFIGURABLE circuits (RCs) are very efficient for information processing tasks [1], such as image and signal processing (e.g., filtering, edge detection, coding, and

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“…Furthermore, there are optimization approaches using integrated DRAM cells [15] and approaches that include nonvolatile techniques like floating gate MOS-FETs [16], spin-torque-transfer cells [17], [18], phase change memories [19], and ferroelectric memories [20]. In addition, the use of ReRAM cells has been suggested [21]- [25].…”

Section: Introductionmentioning

confidence: 99%

Study of Memristive Associative Capacitive Networks for CAM Applications

Nielen

Siemon

Tappertzhofen

et al. 2015

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Resistively switching devices are key enabler for future hybrid CMOS/nano-crossbar array architectures. Due to the availability of nonvolatile states novel reconfigurable in-memory computing approaches become feasible. In particular complementary resistive switches are highly attractive cross-point junction elements due to their inherent sneak path prevention. By applying a nondestructive capacitive readout procedure the complementary resistive switches implement reconfigurable associative capacitive networks. Those networks establish the functionality of content addressable memories and enable memory intensive computing operations for realization of pattern recognition tasks. These are essential for router or network switch applications. In this study a highly accurate physics-based dynamical memristive device model is used to evaluate the network properties for various configurations. The high ON-to-OFF ratio of electrochemical metallization cells beneficially supports the functionality of the network. The voltage margin and energy consumption are analyzed for various crossbar array sizes. Moreover, a test setup to study those networks supported by measurements was developed and proof-of-concept results for a pre-programmed capacitive array are presented.Index Terms-Associative capacitive network (ACN), complementary resistive switch (CRS), content addressable memories (CAM), crossbar array, nondestructive readout, resistive switch.

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Non-volatile one-transistor-cell multiple-valued CAM with a digit-parallel-access scheme and its applications

Cited by 7 publications

References 7 publications

Hybrid self-controlled precharge-free CAM design for low power and high performance

Hybrid self-controlled precharge-free CAM design for low power and high performance

High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing

Study of Memristive Associative Capacitive Networks for CAM Applications

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