Nonvolatile Memory Action Due to Hot-Carrier Charge Injection in Graphene-on-Parylene Transistors

Abstract

We fabricated graphene field-effect transistors (GFETs) with hybrid organic/inorganic gate dielectrics, in which parylene C is used as the organic component. The HOMO−LUMO gap of parylene is large enough to provide effective gate insulation, yet significantly smaller than that of the inorganic component (SiO 2 ) of the dielectric. This allows this polymeric material to serve as an effective "floating node" that may be programmed by applying large voltage pulses to the GFET drain. We identify the role of two types of trapping in these devices: the first is mediated by short-lived interfacial states at the graphene−parylene interface, while the second, which is responsible for the nonvolatile memory function, involves hot-carrier injection into long-lived trap states deep in the parylene layer. Retention measurements demonstrate that charge injected into the parylene interior may be retained over long decay times (months), thereby confirming the potential of graphene-on-parylene for nonvolatile memory implementations.

Ultrahigh On‐Current Density of Organic Field‐Effect Transistors Facilitated by Molecular Monolayer Crystals

“…It is worth mentioning that the calculated temperature is the lattice temperature of the active layer rather than the carrier temperature. [66,67] Although in the graphene FETs where transient current degradation is usually reversible due to the hot-carrier effects and the capture of deep levels, [68][69] the exact degradation mechanisms and the deterioration at different locations of the device required further in-depth studies. Instead of sole channel heating, the heating at contact regions, especially near the source electrode, may be more concentrated and induce more heat damage.…”

Probing the Dynamics of Electric Double Layer Formation over Wide Time Scales (10–9–10+5 s) in the Ionic Liquid DEME-TFSI

“…37,38 As we show in Figure 1b, the two capacitor electrodes were integrated into a (50-Ω matched) coplanar waveguide, allowing us to maintain signal integrity in the transient measurements. 37,38 The capacitors were patterned using a standard electron-beam lithography process, with Cr/ Au (10/190 nm) metallization. Completed chips were mounted on an FR-4 laminate carrier, onto which a micropipette was used to drop DEME-TFSI solution, thereby forming the ionic capacitor (Figure 1a,c).…”

Engineering an Indium Selenide van der Waals Interface for Multilevel Charge Storage

“…The effect of charge impurities present at the InSe/substrate interface is neglectable based on the measurement of the retention times at various V G values from a pristine InSe device (Figure S3). Other possible hysteresis mechanisms, such as hot carrier injection due to a high drain field, 26 do not play a dominant role by comparing the retention time measured at V DS of 1 and 10 V (Figure S4).…”