2010 International Electron Devices Meeting 2010
DOI: 10.1109/iedm.2010.5703401
|View full text |Cite
|
Sign up to set email alerts
|

Normally-off AlGaN/GaN-on-Si MOSHFETs with TaN floating gates and ALD SiO<inf>2</inf> tunnel dielectrics

Abstract: In this work, we have demonstrated a normally-off AlGaN/GaN metal-oxide semiconductor heterojunction field effect transistor (MOSHFET) wherein the enhancement mode operation is enabled by charge storage within a metal floating gate embedded in a dielectric stack and negative charges in the tunnel oxide. By combining ALD SiO 2 and TaN floating gate (FG), up to 6V of V T shift after pulse programming (corresponding ~ 1.2x10 13 charges/cm 2 stored within the FG) is obtained which results in a normally-off device … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
13
0

Year Published

2013
2013
2023
2023

Publication Types

Select...
6
1

Relationship

0
7

Authors

Journals

citations
Cited by 16 publications
(13 citation statements)
references
References 5 publications
0
13
0
Order By: Relevance
“…So far, there are several approaches to realize an enhancement mode operation, such as a recessed gate structure [1] [2], p-GaN gate [3][4] [5], p-AlGaN gate [6], fluoride-based plasma treatment [7], the piezoneutralization layer [8], and floating charges [9], etc. Among these different approaches, the AlGaN/GaN HEMT with either a p-GaN or p-AlGaN gate is a promising candidate for an enhancement mode device.…”
Section: Introductionmentioning
confidence: 99%
“…So far, there are several approaches to realize an enhancement mode operation, such as a recessed gate structure [1] [2], p-GaN gate [3][4] [5], p-AlGaN gate [6], fluoride-based plasma treatment [7], the piezoneutralization layer [8], and floating charges [9], etc. Among these different approaches, the AlGaN/GaN HEMT with either a p-GaN or p-AlGaN gate is a promising candidate for an enhancement mode device.…”
Section: Introductionmentioning
confidence: 99%
“…The values of d 1 , d 2 , and d 3 in this Sentaurus TCAD simulation exercise are set at 4 nm and d 4 is set at 3 nm. The top gate dielectric layer is free from any plasma treatment and serving as a barrier to prevent any electron tunneling in order to reduce the gate leakage current [32].…”
Section: Tcad Simulations On the Proposed Gate Structurementioning
confidence: 99%
“…11 shows the retention characteristic comparisons between experimental floating gate structure and simulated combined recessed gate and floating gate structures. The experimental data are from references [11] and [12]. The different charge densities at different retention time are set in the simulations, respectively, according to the relationship of the charge density changing with the elapsed time from the experimental data.…”
Section: B Combined Recessed Gate and Fixed Insulator Interfacementioning
confidence: 99%