Novel 4&lt;italic&gt;F&lt;/italic&gt;&lt;sup&gt;2&lt;/sup&gt; Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Verma, Shivam; Kaundal, Shalu; Kaushik, Brajesh Kumar

doi:10.1109/tnano.2014.2346790

Cited by 16 publications

(5 citation statements)

References 16 publications

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“…5. [24][25][26][27][28] The vertical BC MOSFET [29][30][31][32][33][34] has some excellent characteristics that are suitable for the STT-MRAM cell design. The high drivability of the vertical BC MOSFET arising from its gate-all-around structure is attributed to excellent gate controllability.…”

Section: Insulatormentioning

confidence: 99%

Cross-point-type spin-transfer-torque magnetoresistive random access memory cell with multi-pillar vertical body channel MOSFET

Sasaki

Endoh

2018

Jpn. J. Appl. Phys.

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In this paper, from the viewpoint of cell size and sensing margin, the impact of a novel cross-point-type one transistor and one magnetic tunnel junction (1T-1MTJ) spin-transfer-torque magnetoresistive random access memory (STT-MRAM) cell with a multi-pillar vertical body channel (BC) MOSFET is shown for high density and wide sensing margin STT-MRAM, with a 10 ns writing period and 1.2 V V DD . For that purpose, all combinations of n/p-type MOSFETs and bottom/top-pin MTJs are compared, where the diameter of MTJ (D MTJ ) is scaled down from 55 to 15 nm and the tunnel magnetoresistance (TMR) ratio is increased from 100 to 200%. The results show that, benefiting from the proposed STT-MRAM cell with no back bias effect, the MTJ with a high TMR ratio (200%) can be used in the design of smaller STT-MRAM cells (over 72.6% cell size reduction), which is a difficult task for conventional planar MOSFET based design.

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Section: Insulatormentioning

confidence: 99%

Cross-point-type spin-transfer-torque magnetoresistive random access memory cell with multi-pillar vertical body channel MOSFET

Sasaki

Endoh

2018

Jpn. J. Appl. Phys.

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“…Berkeley short-channel insulated gate field-effect transistor model of combined multigate (BSIM CMG) [10] is calibrated based on the results acquired from the TCAD device simulations. The BSIM CMG model calibration methodology for vertical GAA operation is similar to that in [2]. Moreover, experimental results for high-performance PMA MTJs [11] from Table I are used to calibrate compact Verilog-A models corresponding to low resistance area product (RA) stack 1 and high RA stack 2.…”

Section: Impact Of High-k Gaa Devicesmentioning

confidence: 99%

“…The details of BSIM model calibration procedure are given in [2]. For ASYM devices, the asymmetry parameters corresponding to ASYMMOD = 1 [10] are used.…”

Section: Appendix Model Calibrationmentioning

confidence: 99%

“…Select devices that provide high current-driving capability at smaller dimensions can enhance the integration density of STT MRAMs while retaining efficient write operation. With this objective, a 4F 2 buried source line (SL) STT MRAM cell with vertical gate all around (GAA) n-channel MOS (nMOS) transistor as select device was presented and analyzed in [2]. The implementation of vertical GAA cell offered significant improvements in terms of cell area and leakage/idle power over planar STT MRAM cells, owing to its structure and excellent gate control.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform

Verma

Kaushik

2016

IEEE Trans. VLSI Syst.

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In recent years, researchers have focused toward reduction in power dissipation and cell size to employ spin-transfer torque (STT) magnetic random-access memories (MRAMs) for embedded applications. Hence, the magnetic tunnel junctions (MTJs) with an optimized structure and magnetic properties are being explored to reduce the switching current. However, the switching current reduction in the MTJs generally lowers the data-retention capability. Hence, a different approach to reduce power dissipation using a novel select device should be considered. This paper, therefore, explores the STT MRAM with vertical silicon nanowire gate all around (GAA) high-k select device for superior performance. The MTJ is stacked above the vertical GAA device, so that both occupy the same footprint area to achieve high array density. Furthermore, enhancement of current drive using high-k gate dielectric and its impact on the STT MRAMs are analyzed at different feature sizes. The proposed STT MRAM cell with high-k dielectric (HfO 2 ) lowers the power dissipation by 8%-25% and increases the write margins (WMs) up to 38%, with negligible increment in delay in comparison with the GAA device using low-k dielectric (SiO 2 ). Moreover, asymmetricity is introduced in device configuration to achieve power savings of 25%-30% at high V DD . The proposed asymmetric high-k cell offers a substantially larger tradeoff window between high WMs and low power dissipation. Index Terms-High-k dielectric, magnetic random-access memories (MRAMs), nanowire (NW), perpendicular magnetic anisotropy (PMA), spin-transfer torque (STT).Shivam Verma received the B.E. degree in electronics and communication engineering from the Shri Vaishnav Institute of Technology and Science at Indore, Indore, India, in 2010, and the M.Tech. degree in microelectronics from IIT Varanasi, Varanasi, India, in 2012. He is currently pursuing the Ph.D. degree with IIT Roorkee, Roorkee, India.His current research interests include spin transfer torque-based devices and all spin logic devices.Brajesh Kumar Kaushik (SM'13) received the B.E. degree in electronics and communication engineering from D. C. R

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“…These parameters are obtained or calculated from the experimental data in [3]. The difference between IW and I C0 is referred to as write margin (WM) (microampere) in this paper [15].…”

Section: A Model Calibrationmentioning

confidence: 99%

Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS

Verma

Pal

Mahawar³

et al. 2016

IEEE Trans. Electron Devices

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Conventional spin transfer torque (STT) magnetoresistive random access memory (MRAM) generally includes a bulk n-channel MOS (NMOS) transistor as an access device that provides equal drive current in standalone conditions in both the directions. However, the switching current requirement of magnetic tunnel junctions (MTJs) in STT MRAM is highly asymmetric (2 to 3:1). With conventional access devices, the excess write current in one direction maps to unnecessarily higher power dissipation. Hence, in this paper, a novel STT MRAM cell with an asymmetric-dielectric (asymmetric-k) sidewall-spacer NMOS (ASNMOS) is presented. ASNMOS has different-k sidewall spacers, i.e., one side high-k and other side low-k spacer. As desired, this novel ASNMOS provides asymmetric drive current and reduces the overall power dissipation. The proposed STT MRAM cell is analyzed with HSPICE simulations using calibrated Verilog-A models for access device and perpendicular magnetic anisotropy MTJ. The STT MRAM cell with the proposed ASNMOS exhibits up to 25% reduction in the dynamic power dissipation over the STT MRAM cell with the conventional symmetric NMOS as an access device. Moreover, ASNMOS-based cells shows higher reliability wherein the worst case current density through MTJ is reduced by 25%. IndexTerms-Asymmetric-k sidewall-spacer NMOS (ASNMOS), HfO 2 spacer, magneto-resistive random access memory (MRAM), spin transfer torque (STT), write margin (WM).

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Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Cited by 16 publications

References 16 publications

Cross-point-type spin-transfer-torque magnetoresistive random access memory cell with multi-pillar vertical body channel MOSFET

Cross-point-type spin-transfer-torque magnetoresistive random access memory cell with multi-pillar vertical body channel MOSFET

Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform

Performance Enhancement of STT MRAM Using Asymmetric- Sidewall-Spacer NMOS

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