Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO<sub>2</sub>–Based High-k Dielectrics

Lee, Jongmin; Park, Dong-Sik; Yew, Seung-chul; Shin, Seungyong; Noh, Junyong; Kim, Hyoung-Sub; Choi, Byoungdeog

doi:10.1109/led.2017.2755050

Cited by 16 publications

(5 citation statements)

References 13 publications

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“…These problems primarily stem from complex capacitor structures with high aspect ratios. Despite attempts to improve capacitor technology by incorporating high-k dielectric materials and three-dimensional structures, these approaches result in increased production costs and added complexity [5][6][7] .…”

Section: Introductionmentioning

confidence: 99%

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Kim,

et al. 2024

Preprint

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Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Here, we propose a novel Schottky barrier memory (SBRAM) featuring a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

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Section: Introductionmentioning

confidence: 99%

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Kim,

et al. 2024

Preprint

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“…The scaling down of dynamic random-access memory (DRAM) cell has been continuously required for high-density, high-speed, and low-power operations [ 1 – 3 ] However, the conventional one transistor-one capacitor (1T- 1C) DRAM is facing an inevitable problem: it is increasingly difficult to achieve the required capacitance to differentiate the two states (~ 10 fF/cell) with the smaller cell area [ 4 ]. Even though there have been many studies to improve the capacitor technologies, such as new high- k materials [ 5 – 7 ] and a high-aspect-ratio 3D capacitor structure [ 8 , 9 ], these approaches possess the issue of increasing fabrication complexities and high cost [ 2 , 3 ]. To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based random-access memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [ 10 – 16 ].…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

et al. 2022

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Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (VGC,ST) and anode–cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of − 0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate–cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

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“…The scaling down of dynamic random-access memory (DRAM) cell has been continuously required for high-density, high-speed, and low-power operations [1][2][3] However, the conventional one transistor-one capacitor (1T-1C) DRAM are facing an inevitable problem: it is increasingly di cult to achieve the required capacitance to differentiate the two states (~ 10 fF/cell) with the smaller cell area [4]. Even though there have been many studies to improve the capacitor technologies, such as new high-k materials [5][6][7] and a high-aspect-ratio 3D capacitor structure [8,9], these approaches possess the issue of increasing fabrication complexities and high cost [2][3]. To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based random-access memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

Kim

Cho

Kwak

et al. 2021

Preprint

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Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.55 V shows the continuous data retention capability without refresh operation with a low standby current of 0.13 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on the adjacent unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

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Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO₂–Based High-k Dielectrics

Cited by 16 publications

References 13 publications

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

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Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO2–Based High-k Dielectrics

Cited by 16 publications

References 13 publications

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

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Novel Approach for the Reduction of Leakage Current Characteristics of 20 nm DRAM Capacitors With ZrO₂–Based High-k Dielectrics