Novel approach to reduce power droop during scan-based logic BIST

Omaña, M.; Rossi, Daniele; Fuzzi, F.; Metra, C.; Tirumurti, C.; Galivache, R.

doi:10.1109/ets.2013.6569375

Cited by 5 publications

(2 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our approach is somehow similar to re-seeding techniques (e.g., that in [22]), to the extent that the sequence of test vectors is properly modified in order to fulfill a given requirement that, however, is not to increase FC (as it is usually the case for reseeding), but to reduce PD. The basic idea behind our approach (in its non-scalable version) was introduced in [23].…”

Section: Introductionmentioning

confidence: 99%

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Omaña

Rossi

Fuzzi

et al. 2017

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel, scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the Logic BIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target Fault Coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared to recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC.

show abstract

Section: Introductionmentioning

confidence: 99%

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Omaña

Rossi

Fuzzi

et al. 2017

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…In [19], we recently proposed an approach to reduce PD at capture in scan-based LBIST adopting the LOC scheme. It enables to reduce PD at capture up to the 50% compared to conventional scan-based LBIST by replacing one test vector of the test sequence with a substitute test vector that increases the correlation between the test vectors applied at following capture cycles.…”

Section: Introductionmentioning

confidence: 99%

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

Omaña

Rossi

Beniamino

et al. 2015

IEEE Trans. Comput.

View full text Add to dashboard Cite

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/).In case of abuse or copyright appearing without permission e-mail repository@westminster.ac.uk Abstract-During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as LowCost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar ...

show abstract

On the Switching Activity in Faulty Circuits During Test Application

Pomeranz

Reddy

2016

2016 IEEE 25th Asian Test Symposium (ATS)

View full text Add to dashboard Cite

Novel approach to reduce power droop during scan-based logic BIST

Cited by 5 publications

References 18 publications

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST

On the Switching Activity in Faulty Circuits During Test Application

Contact Info

Product

Resources

About