Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

Bernard, E.; Ernst, T.; Guillaumot, B.; Vulliet, N.; Barral, V.; Maffini-Alvaro, V.; Andrieu, F.; Vizioz, C.; Campidelli, Y.; Gautier, P.; Hartmann, J.-M.; Kies, R.; Delaye, V.; Aussenac, F.; Poiroux, T.; Coronel, P.; Souifi, Abdelkader; Skotnicki, T.; Deleonibus, S.

doi:10.1109/vlsit.2008.4588546

Cited by 28 publications

(19 citation statements)

References 3 publications

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“…Examples of gate all around devices based on multichannel FinFETs have been demonstrated in a quasi 3D configuration. This enhances the saturation current and maintains a very low leakage current [50][51][52][53][54] (Figures 11, 12 and 13). Gate all around ultimate 3D nanowires have been obtained using a top down approach [51,54].…”

Section: Multigate Devicesmentioning

confidence: 99%

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Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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The nanoelectronics industry is facing historical challenges to scale down CMOS devices to meet demands for low voltage, low power, high performance and increased functionality. Using new materials and devices architectures is necessary. HiK gate dielectrics and metal gates have been introduced and have shown their ability to reduce power consumption. Fully depleted ultra-thin SOI devices are a good alternative to bulk for low power applications. Multigate devices are the current goal in device architecture to increase MOSFET drivability, reduce power, and allow new opportunities for future applications. Thin film based solutions will be necessary in the future because of fundamental limitations on gate capacitance scaling and system integration requirements. Exploiting 3D device stacking via wafer bonding could be a good way to introduce new materials (HiK, strained Si, hybrid orientations, Ge, III-Vs, Carbon-based materials, graphene and CNTs, and functional molecules) and continue increasing integration density. Si based CMOS will be scaled beyond the ITRS as the System-on-Chip/Wafer Platform.The international technology roadmap of semiconductors (ITRS) [1] distinguishes three types of products: high performance (HP), low operating power (LOP) and low standby power (LSTP) devices. In the HP case, a landmark has been reached at the 32-nm node: the contribution from static power dissipation approaches the dynamic power contribution [2]. Multigate devices could improve this somewhat by increasing the saturation current to leakage current ratio.In this review, we will first analyze the primary limitations and showstoppers of CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new device architectures (FDSOI or multigate devices) are discussed.Low power consumption and heterogeneous function integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, require the leveraging of 3D IN package or ON chip co-integration. Limitations, showstoppers and opportunities of Si CMOS scalingCMOS device engineering consists of minimizing leakage current and the maximization of output current. In sub-100-nm CMOS devices, non-stationary transport is more important than diffusive transport. To this end, several questions arise related to the origins of the leakage currents, non-stationary transport limitations and supply voltage scaling.

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Section: Multigate Devicesmentioning

confidence: 99%

“…ds (V G ) characteristics of multi-channel FETs (MCFET), which allow for a substantial reduction in I off and increase in Ion[53].…”

mentioning

confidence: 99%

Ultra-thin films and multigate devices architectures for future CMOS scaling

Deleonibus

2011

Sci. China Inf. Sci.

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“…Reported performance of 50 nm NMOS with TiN/Hf0 2 gate stack reached /ON = 2.27 mA/μπι, 7 0 FF = 16.4 ρΑ/μηι, and S = 63 mV/decade. 19,20 • Variability Silicon-on-insulator devices can also be interesting for reducing the variability in decananometer MOSFETs, which also represents a major challenge at the end of the roadmap. The sources of local and inter-die threshold voltage Vj variability in undoped ultra-thin FD-SOI MOSFETs with a high-K/metal stack have been Figure 11.…”

Section: • Multi-gate Devicesmentioning

confidence: 99%

“…Multi-channels realized using SON technology leading to very high drain currents with excellent control of leakage currents. 20 experimentally investigated and discriminated. Charges in the gate dielectric and/or TiN gate workfunction fluctuations have been found to be major contributors to the local V T variability, whereas SOI thickness variations have a negligible impact down to í s ¡ = 7 nm.…”

Section: • Multi-gate Devicesmentioning

confidence: 99%

Silicon‐Based Devices and Materials for Nanoscale CMOS and Beyond‐CMOS

Luryi

Xu²,

Zaslavsky³

2010

Future Trends in Microelectronics

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At the end of the ITRS, new materials, nanotechnologies and device architectures will be needed for nanoscale CMOS and beyond-CMOS. Silicon-on-insulator (SOI)-based devices are promising for the ultimate integration of electronic circuits on silicon [1]. We will discuss a number of key issues, including: the performance of single-and multi-gate thin film MOSFETs; the comparison between Si, Ge and III-V SOI channels; the effects of strain, high-κ materials, and Schottky source-drain (S/D) contacts. We then proceed to beyond-CMOS nanodevices based on nanowires or tunnel FETs and, finally, to an overview of advanced memory architectures on the nanoscale.Strained SOI is very interesting for boosting performance, with electron and mobilities enhanced by uniaxial tensile and compressive strains respectively, down to ultrathin channels [2]. Schottky S/D engineering is also promising for nanoscale CMOS, with PtSi/Si contacts producing record current drive and RF performance in p-channel SOI MOSFETs [3]. In the high-κ arena, the product of κ and the energy barrier that determines the gate leakage current can be set lower for double-gate (DG) SOI than bulk CMOS, offering a wider choice of gate dielectrics [4]. Multi-gate architectures based on volume inversion are expected to provide higher current drive down to sub-10nm gate lengths [5]. Further out, multi-bridge-channel MOSFETs [6] and gate-all-around SOI nanowires with tunable thresholds [7] represent the ultimate integration of innovative nanodevices with promising electrical properties.In the advanced memory arena, we will discuss capacitorless one-transistor DRAMs [8] and various variants of FinFlash memories that offer good downscaling prospects [9]. Independent DG FinFETs are also candidates for enhanced SRAM performance due to lower leakage and better noise margins [10]. Finally, there are promising tunneling FET candidates that may provide sharp switching for beyond-CMOS low-power applications, including DG high-κ TFETs, strain Ge DG with asymmetric source/drain and feedback TFETs [11][12][13].

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“…Threedimensional multigate structures should satisfy the requirements since they combine a high current drivability due to the 3-D integration of vertically stacked channels and excellent short-channel-effect immunity, thanks to the multigate control of the Si channels [1]- [5]. Excellent 3-D multichannel CMOSFETs (MCFETs) [1], [4]. However, due to their 3-D configuration, high gate-source/drain (S/D) capacitances are generated in such structures, degrading the dynamic performances and the CV /I ratio.…”

Section: Introductionmentioning

confidence: 99%

First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

Bernard

Ernst

Guillaumot

et al. 2009

IEEE Electron Device Lett.

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For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV /I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I ON /I OFF characteristics (NMOS: 2.33 mA/μm at 27 pA/μm and PMOS: 1.52 mA/μm at 38 pA/μm). A gate capacitance C gg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI (= g m /g ds ) is improved by 92%.Index Terms-A VI , C gg , CV /I, high performances, internal spacers, low standby power, multichannel CMOSFETs (MCFETs), 3-D.

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Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack

Cited by 28 publications

References 3 publications

Ultra-thin films and multigate devices architectures for future CMOS scaling

Ultra-thin films and multigate devices architectures for future CMOS scaling

Silicon‐Based Devices and Materials for Nanoscale CMOS and Beyond‐CMOS

First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

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