Novel Linearization Technique for Low-Distortion High-Swing CMOS Switches with Improved Reliability

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

Tavares

et al. 2008

Self Cite

-This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm 2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of -79 dB and an ENOB better than 12 bits can be reached without self-calibration.

Section: Circuit Implementation and Simulation Resultsmentioning

confidence: 99%

Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC

Esperanca

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

Tavares

et al. 2008

Self Cite

“…The basic idea behind the SLC circuits, initially described by the authors in [10], consists of attenuating the gate-tosource voltage and conductance of the NMOS switch (g nmos ) when a low voltage is applied to the input (v in ), and amplifying them for higher voltages in the input (solid lines shown in Fig. 1).…”

Section: Review Of the Existing Switch-linearization Techniques And Pmentioning

confidence: 99%

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

Galhardo

Analog Integr Circ Sig Process

Paulino

2009

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This paper describes the efficient design of an improved and dedicated switchedcapacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

“…Each ATG switch is driven by a dedicated switch linearization control (SLC) circuit, described in detail in [5]. The complete schematic of the SLC circuit, is shown in Fig.…”

Section: B the Passive Front-end Sample-and-hold Circuitsmentioning

confidence: 99%

“…The main transistors M 1 and M 2 form the CMOS switch, and are respectively sized with aspect ratios of 20/0.12 and 80/0.12. Their controlled gate voltages are function of the input voltage, v in , resulting in very highly linear switch without having any reliability problems [5]. Note that the fact of connecting the MDAC sampling capacitors, C S , charged with the input signal of the previous sample to the passive S/H, C SH , only causes a low-pass filtering function of the type )))…”

Section: B the Passive Front-end Sample-and-hold Circuitsmentioning

confidence: 99%

“…This amplifier employs local-feedback in order to achieve constant closed-loop gain against ProcessSupply-Temperature (PVT) variations and thus, avoiding the need of any digital self-calibration or gain-control techniques. Time skews between the 2 channels are highly reduced, by using two passive front-end Sample-and-Hold (S/H) circuits, with dedicated switch-linearization control (SLC) circuits [5], driven by a single clock phase [6]. Simulations reach a peak SNDR of 34 dB, a SFDR of 47 dB, a THD of -43 dB and 5.35-bit ENOB, for a power dissipation of 20 mW which corresponds to an energy efficiency better than 0.5 pJ per conversion.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

Galhardo

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

Paulino

2008

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Abstract-A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-andHold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.