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Abstract-A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-andHold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.

This paper presents a programable perturbat i on and observation control i mplementation for a w i nd generation system and its power electron i c converter. The obj ective of the method i n th i s particular appl i cation i s to adjust the power del i vered to charge a battery to its max i mum and allowable value, function of the real values of several parameters and the i r cont i nuous var i ation, the most i mportant the w i nd velocity and the turb i ne efficiency. Also, to i mprove the power throughput and to use the turb i ne and generator marginal zones of operation, an unusual power converter i s used, allow i ng a wide range for the i nput voltage values. The i mplemented control i s cont i nuously measur i ng the actual power and looks for a new and powerful operation po i nt.

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-This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm 2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of -79 dB and an ENOB better than 12 bits can be reached without self-calibration.