Design of low-voltage low-power pipeline ADCs using a single-phase scheme

Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

“…2. The single-phase technique described in [6] is used and, hence, only one clock phase is used, φ 1 , and it complementary version, φ 1n . These complementary phases are used to drive the two S/H blocks and all 1.5-bit MDACs.…”

“…This amplifier employs local-feedback in order to achieve constant closed-loop gain against ProcessSupply-Temperature (PVT) variations and thus, avoiding the need of any digital self-calibration or gain-control techniques. Time skews between the 2 channels are highly reduced, by using two passive front-end Sample-and-Hold (S/H) circuits, with dedicated switch-linearization control (SLC) circuits [5], driven by a single clock phase [6]. Simulations reach a peak SNDR of 34 dB, a SFDR of 47 dB, a THD of -43 dB and 5.35-bit ENOB, for a power dissipation of 20 mW which corresponds to an energy efficiency better than 0.5 pJ per conversion.…”