Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS

He, Qian; Yan, Aibin; Lai, Chaoping; Zhang, Yinlei; Liu, Chunming; Chen, Zhile; Wu, Zhengying; Cui, Jie; Liang, Hongbin

doi:10.1109/iscas.2018.8351008

Cited by 5 publications

(2 citation statements)

References 27 publications

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“…In recent years, the latch structure of double node upset (DNU) immunity has become one of the hot spots in sequential logic circuit radiation hardening design. Researchers have proposed a variety of radiation-hardened latch structures to mitigate DNUs [18][19][20][21][22][23][24]. A typical structure is a double node upset tolerant (DONUT) latch [25], which comprises four dual interlocked storage cells (DICEs) in a multi-interlocked scheme where each DICE cell is always guaranteed two stable nodes, rendering the DONUT latch resilient to DNUs.…”

Section: Introductionmentioning

confidence: 99%

A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications

Wang

Guo

et al. 2023

Electronics

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This paper presents a novel double node upset (DNU) self-recoverable and single event transient (SET) pulse filterable latch design in 28 nm CMOS technology. The loop structure formed by C-elements (CEs) ensures that the latch can self-recover from the DNUs. A Schmitt trigger at the output can filter out transient pulses from anywhere in the circuit. A clock-controlled inverter channel that connects the input to the output reduces the transmission latency. The simulation results show that the proposed design is completely immune to DNUs, and the delay power area product (DPAP) is reduced by more than 50% compared with the previous design.

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Section: Introductionmentioning

confidence: 99%

A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications

Wang

Guo

et al. 2023

Electronics

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“…In order to effectually alleviate the DNU issue, many attempts have been made by researchers to find efficient solutions. As a result, some proposals of DNU-tolerant latches have appeared in recently published papers [11][12][13][14][15][16][17][18][19][20][21]. The DNCSEIL latch [11] is DNU tolerant but cannot restore from DNUs.…”

Section: Introductionmentioning

confidence: 99%

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology

Yan

Zhou

Wei

et al. 2022

Proceedings of the Great Lakes Symposium on VLSI 2022

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With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input Celements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively. CCS CONCEPTS• Hardware → Circuit hardening; Latch design; Transient errors and upsets; Fault tolerance.

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Multiple Node Upset-Tolerant Latch Design

Liu

2019

IEEE Trans. Device Mater. Relib.

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Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS

Cited by 5 publications

References 27 publications

A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications

A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology

Multiple Node Upset-Tolerant Latch Design

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