Novel low delay slew rate control I/Os

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

“…These hazards will become even worse if the nanomerer CMOS technology is used and PVT variations appear [13][14][15][16]. However, most of the prior designs did not consider the slew rate deviation caused by the PVT variation [17][18][19][20][21][22]. In fact, PVT variations have been proved to affect the slew rate of the output buffer severely, as shown in Fig.…”