Novel Materials and Processes in Replacement Metal Gate for Advanced CMOS Technology

Bao, Ruqiang; Hung, Steven; Wang, Miaomiao; Chung, Kisup; Barman, Soumendra N.; Krishnan, Siddarth; Yang, Yihang; Tang, Wenlong; Li, Luping; Lin, Y. M.; Chan, Michael; Chen, Zhebo; Miao, Xin; Hopstaken, Marinus; Conti, Richard; Jagannathan, H.; Chudzik, M.; McHerron, D.; Haran, Bala; Natarajan, S.

doi:10.1109/iedm.2018.8614524

Cited by 7 publications

(9 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Equivalent oxide thickness is 1.0 nm, consisting of SiO 2 (0.7 nm) and HfO 2 (1.7 nm). Metal gate resistivity (ρ MG ) is 2000 Ω•μm, which is the same as TiAl, n-type workfunction metal [18], [19], and low-k dielectric constant is 9.0. Operation voltage (V DD ) is fixed to 0.7 V. Fig.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…C gd0 and C jd are extracted first using eqs. (18) and (19), respectively. C gs0 and C js are extracted using Im(Y 12 int ) and Im(Y 22 int ) at the V ds of 0 V. Then, C gb0 is extracted using eq.…”

mentioning

confidence: 99%

“…Assuming the second-order terms (ω 2 ) in the denominator and the higher-order terms (ω 3 , ω 4 , ω 5 ) are negligible at low frequency, real and imaginary parts of Y int to extract the parameters in Fig. 13a are 17 18 19 20 . These components are equivalent to those for conventional MOSFETs at off state [36].…”

mentioning

confidence: 99%

See 2 more Smart Citations

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

View full text Add to dashboard Cite

Analog/RF performances of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) and nanosheet FETs (NSFETs) were investigated and compared thoroughly using fully-calibrated TCAD. NSFETs have greater current drivability and gate-to-channel controllability than FinFETs under the same footprint, thus achieving larger intrinsic gain. But the cutoff frequencies (F t) of FinFETs and NSFETs are comparable due to larger gate capacitances (C gg) of NSFETs compensating DC performance improvements. Gate resistances (R g) of NSFETs are larger because of their metal gate (MG) configuration surrounding the channels, longer MG height by the topmost NS spacing region, and the bottom transistor, thus degrading maximum oscillation frequency (F max). Device design guidelines of FinFETs and NSFETs are also studied for better intrinsic gain, F t , and F max. Intrinsic gain is improved by better electrostatics, whereas F t increases by greater current drivability over C gg. For larger F max , careful device design is required to compensate between R g , C gg , output resistance, and F t. Overall, NSFETs outperform FinFETs in terms of intrinsic gain, F t , and F max , thus NSFETs are promising for analog/RF applications.

show abstract

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Yoon

Baek

2020

IEEE Access

View full text Add to dashboard Cite

show abstract

“…In advanced CMOS technology, in order to reduce the influence of the thermal budget on junction and channel quality, introducing the novel materials and processes are necessary in gate engineering. Therefore, the dipole formation in the gate stack is widely applied in the Replacement Metal Gate (RMG) process [168,169,170,171,172,173]. Usually, Lanthanum (La) and Aluminum (Al) are used to tune threshold voltage for NFET and PFET due to the different dipole polarity [168,169,170,171].…”

Section: Reliabilitymentioning

confidence: 99%

“…The CMOS integration flow together with a mechanism for PBTI improvement, which are shown as a band diagram in Figure 27b. For the reliability study, the impurity implantation in the HK&MG stack, such as “Nitrogen Implantation” in the work function metal layer [170] and the thickness tuning of an effective work function metal (EWF) can be investigated [170,171,172,173]. The advantage of such a study is to control the V T shift over a processed wafer, which provides very valuable information for chipmakers.…”

Section: Reliabilitymentioning

confidence: 99%

Miniaturization of CMOS

Radamson

Zhang

et al. 2019

Micromachines

View full text Add to dashboard Cite

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

show abstract

Decreasing Interface Defect Densities via Silicon Oxide Passivation at Temperatures Below 450 °C

Rad

Lehtiö

Mack

et al. 2020

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

Low-temperature (LT) passivation methods (< 450 o C) for decreasing defect densities in the material combination of silica (SiOx) and silicon (Si) are relevant to develop a diverse technology (e.g. electronics, photonics, medicine), where defects of SiOx/Si cause losses and malfunctions. Many device structures contain the SiOx/Si interface(s), of which defect densities cannot be decreased by the traditional, beneficial high temperature treatment (> 700 o C). Therefore, the LT passivation of SiOx/Si has been, since long, a research topic to improve applications performance. Here, we demonstrate that a LT (< 450 o C) ultrahigh-vacuum (UHV) treatment is a potential method that can be combined with current state-of-theart processes in a scalable way, to decrease the defect densities at the SiOx/Si interfaces. The studied LT-UHV approach includes a combination of wet chemistry followed by UHV-based heating and pre-oxidation of silicon surfaces. The controlled oxidation during the LT-UHV treatment is found to provide an until now not reported crystalline Si oxide phase. This crystalline SiOx phase can explain the observed decrease in the defect density by halve.Furthermore, the LT-UHV treatment can be applied in a complementary, post-treatment way to ready components to decrease electrical losses. The LT-UHV treatment has been found to decrease the detector leakage current by factor of two.

show abstract

Novel Materials and Processes in Replacement Metal Gate for Advanced CMOS Technology

Cited by 7 publications

References 0 publications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications

Miniaturization of CMOS

Decreasing Interface Defect Densities via Silicon Oxide Passivation at Temperatures Below 450 °C

Contact Info

Product

Resources

About