Novel Palladium Germanide Schottky Contact for High Performance Schottky Barrier Ge MOSFETs and Characterization of Its Leakage Current Mechanism

Abstract

The leakage current mechanism of Palladium (Pd) germanide Schottky contact on n-type Ge-on-Si substrate is analyzed in depth. The electric field dependent analysis shows that the dominant leakage current mechanism is the Poole-Frenkel emission due to the existence of deep level traps in the depletion region of the Pd germanide/n-type Ge Schottky diode. The analysis of the dependence of leakage current on temperature also shows that the Poole-Frenkel emission and generation current are the dominant components below 100 degrees C and that the Schottky emission related to thermionic emission of majority carriers over a potential barrier is the main cause of this dominance at high temperature region.

Novel Ni silicide formed with a Ni/Er/Ni/TiN structure for thermal stable and low contact resistance source/drain in MOSFETs

“…At low temperature, the activation energies of all structures are similar to each Schottky barrier height, which suggests that the Schottky emission is the dominant mechanism in the leakage current. 36) However, at high temperatures, the activation energies of the Ni/TiN and Ni/Er/Ni/TiN (4/2/9/10 nm) structures decreased significantly and the leakage current did not track with the Schottky emission mechanism while those of the Er/Ni/TiN and Ni/Er/Ni/TiN (2/2/11/10 nm) structures rarely changed. The decrease in activation energy…”

Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors

“…to overcome fundamental limitations of dimensional scaling. [1][2][3][4] Among these materials, III-V materials (GaAs, InP, GaN, InGaAs, etc.) have attracted a lot of attentions due to their high electron mobility.…”

“…have attracted a lot of attentions due to their high electron mobility. [1][2][3][4] However, the most difficult and long-standing problem of III-V CMOS technology is the lack of a stable gate insulator with minimal interfacial defects between the deposited gate insulators and semiconductor channel materials. 3,4 Introduction of atomic layer deposition (ALD) technology with high-k dielectrics can potentially mitigate this problem and make it possible for the III-V channels to be realized in the III-V MOSFET.…”