Novel procedure to improve LDMOS ESD characteristics by optimizing drain structure

Komatsu, Kanako; Takahashi, Katsutoshi; Sakurai, Tadaomi; Ikimura, Takehito; Shimizu, Masaki; Kimura, Koji; Matsuoka, F.

doi:10.1109/ispsd.2016.7520807

Cited by 8 publications

(1 citation statement)

References 4 publications

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“…However, the BV of the interdigitated LDMOS is reduced due to the curvature effect and high electric field in the terminal region. To suppress the curvature effect, Komatsu et al proposed a novel LDMOS by increasing the curvature radius in the terminal region, [4] but its manufacturing cost increases with device size increasing. To reduce the electric field in the terminal region, Lee et al optimized the LDMOS by inserting P-type rings around the source fingertip region, [5] but the BV could not be improved remarkably by this method.…”

Section: Introductionmentioning

confidence: 99%

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness*

Xu¹,

He²,

Liang³

et al. 2021

Chinese Phys. B

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A novel terminal-optimized triple RESURF LDMOS (TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolar-CMOS-DMOS (BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage (BV) and electrostatic discharge (ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse (TLP) tests, direct current (DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance (R on,sp) of 6.99 Ω⋅mm2. Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

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Section: Introductionmentioning

confidence: 99%