Novel room-temperature first-level packaging process for microscale devices

Zhang, Wen-Yue; Labukas, Joseph P.; Tatić-Lučić, Svetlana; Larson, Lyndon; Bannuru, Thirumalesh; Vinci, Richard P.; Ferguson, Gregory S.

doi:10.1016/j.sna.2005.03.008

Cited by 23 publications

(7 citation statements)

References 15 publications

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“…This disparity may be explained by considering surface roughness of the silicone materials. The surface roughness of gold on the compliant silicone is twice that of gold on the stiff silicone [8]. The difference is clear in the SEM micrographs shown in Figure 3.…”

Section: %mentioning

confidence: 91%

How Stretchable Can We Make Thin Metal Films?

et al. 2005

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Thin metal films deposited on elastomeric substrates can remain electrically conducting at tensile strains up to ~∼00%. We recently used finite-element simulation to explore the rupture process of a metal film on an elastomer. The simulation predicted the highest stretchability on stiff elastomeric substrates [1]. We now report experiments designed to verify this prediction. A ∼15-μm thick silicone elastomer layer with Young's modulus E ∼ 160 MPa is deposited on a 1mm thick membrane of polydimethylsiloxane (PDMS), a silicone elastomer with E ∼3 MPa. Metal stripes consisting of 25-nm thick gold (Au) film sandwiched between two 5-nm thick chromium (Cr) adhesion layers are fabricated either on top of the stiff layer spun onto the soft membrane substrate, or are encapsulated at the interface between the two elastomers. Encapsulated gold films remain electrically conducting beyond 40% strain. But conductors deposited on top of stiff elastomer lose conduction at strains of 3-8%. These results suggest that, in addition to the stiffness of the elastomeric substrate, the initial microstructure of the metal film plays a role in determining its stretchability.

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Section: %mentioning

confidence: 91%

How Stretchable Can We Make Thin Metal Films?

et al. 2005

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“…Namely, they avoid the requirement for an ultra-high vacuum and the problems related to III-V oxides, but also enable relatively low processing temperatures and therefore low residual stresses in the assembly [159,[163][164][165]. In addition, the use of monolayers and/or hydrophilic dielectric layers can relax the requirements for surface smoothness of the wafers [166,167]. Finally, we note that III-V wafer bonding can also be accomplished using sulphide-treated surfaces [168][169][170], but these methods are not covered here.…”

Section: Wafer Bonding Techniques For Long Wavelength Infraredmentioning

confidence: 99%

Optically pumped VECSELs: review of technology and progress

Guina

Rantamäki

Härkönen

2017

J. Phys. D: Appl. Phys.

205

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“…The < 5 nm-thick interface is much thinner than that of BCB bonding and should not disrupt the transfer of light between the substrates or the electrical conductivity across the interface [23]. At the same time, the few-nm interface may relax the surface roughness requirements that are imposed by direct bonding [24]. SAM-assisted bonding of two silicon wafers was previously reported [25].…”

Section: Introductionmentioning

confidence: 98%

Self-assembled monolayer assisted bonding of Si and InP

Bakish¹,

Artel²,

Ilovitsh³

et al. 2012

Opt. Mater. Express

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A versatile procedure for the low-temperature bonding of silicon and indium-phosphide to silicon is proposed and demonstrated. The procedure relies on the deposition and functionalization of self-assembled, single molecular layers on the surface of one substrate, and the subsequent attachment of the monolayer to the surface of the other substrate with or without its own monolayer coating. The process is applicable to the fabrication of hybrid-silicon, active photonic devices.

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Novel room-temperature first-level packaging process for microscale devices

Cited by 23 publications

References 15 publications

How Stretchable Can We Make Thin Metal Films?

How Stretchable Can We Make Thin Metal Films?

Optically pumped VECSELs: review of technology and progress

Self-assembled monolayer assisted bonding of Si and InP

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