Novel silicon-on-insulator lateral power device with step width drift region

Yao, Jiafei; Guo, Yufeng; Zhang, Jun; Lin, Hong; Xia, Xiao-juan

doi:10.1016/j.spmi.2015.05.027

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…For overcoming charge mismatch in SJ structure, the p‐pillars in the vertical DMOS are replaced by the oxide‐bypassed and gradient oxide‐bypassed structure, which appears to be less sensitive to the charge imbalance, obtaining the comparable performance [18, 19]. In addition, the step width drift regions are utilised with the oxide to form a charge compensation between them to achieve a better device performance [20]. However, it can be concluded that these structures still suffer the premature breakdown because of the high electric field at the end of the drift region.…”

Section: Introductionmentioning

confidence: 99%

Improving breakdown performance for SOI LDMOS with sidewall field plate

Tang

Wang

Bao

et al. 2019

Micro & Nano Letters

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In this work, a silicon-on-insulator (SOI) lateral diffused MOSFET (LDMOS) incorporated with sidewall field plate (SEP) is presented and investigated using three-dimensional numeric simulation. A new additional electric field peak is formed, due to the compound field plate established along the n-drift region. The lateral surface electric field can be modulated, which enhances the breakdown voltage. Meanwhile, the doping concentration of n-drift region is increased, which decreases the specific on-resistance. Compared with the superjunction LDMOS, a 23.7% increase in the breakdown voltage and a 21.7% decrease in the specific on-resistance are obtained in the SFP-LDMOS device.

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Section: Introductionmentioning

confidence: 99%

Improving breakdown performance for SOI LDMOS with sidewall field plate

Tang

Wang

Bao

et al. 2019

Micro & Nano Letters

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“…To modulate the electric field in 3-D and improve the BV, the step width (SW) technique is proposed [18], [19]. The structure of the SOI lateral power device with SW technique and high-k dielectric (SWHK device) is shown in Fig.…”

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confidence: 99%

Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-${k}$ Dielectric

Yao

Guo

Yang

et al. 2019

IEEE Trans. Electron Devices

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An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high-k dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high-k dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device. Index Terms-Analytical model, breakdown voltage (BV), high-k, silicon-on-insulator (SOI), step width (SW). I. INTRODUCTION T HE silicon-on-insulator (SOI) lateral power device is widely used in intelligent power applications due to its high breakdown voltage (BV), high speed, small resistance, and reduced leakage current [1]-[5]. In order to improve the BV, an effective approach is to introduce several additional electric field peaks in the drift region, the structures including step doped (SD) drift region [6], [7], step thickness (ST) drift region [8], [9], step buried (SB) oxide layer [10], [11], and variable-k dielectric [12], [13]. With the proposal of Manuscript

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