Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-${k}$ Dielectric

Abstract

An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high-k dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high-k dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device. Index Terms-Analytical model, breakdown voltage (BV), high-k, silicon-on-insulator (SOI), step width (SW). I. INTRODUCTION T HE silicon-on-insulator (SOI) lateral power device is widely used in intelligent power applications due to its high breakdown voltage (BV), high speed, small resistance, and reduced leakage current [1]-[5]. In order to improve the BV, an effective approach is to introduce several additional electric field peaks in the drift region, the structures including step doped (SD) drift region [6], [7], step thickness (ST) drift region [8], [9], step buried (SB) oxide layer [10], [11], and variable-k dielectric [12], [13]. With the proposal of Manuscript

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

“…The technique to realize the highk dielectric pillars in the drift region has been discussed in Refs. [12,14]. After etching the trenches, the high-k dielectric is deposited into the trenches by pulsed-laser deposition.…”

“…according to the continuances of the potential, electric field, and doping at the interface of the high-k and silicon region. [13] Solving the 3D Poisson equation for the Gaussian box under the boundary conditions, [14] the potential expression and electric field expression at the x-direction along the AA line is derived as…”

“…The electric field could be improved and the doping profile could be modulated due to the assistant depletion of the high-k dielectric pillars, which results in an improvement of the BV and reduction of the R on,sp . [11][12][13][14] With the employed side high-k dielectric into the SD device, the electric field is further modulated and a higher BV and higher doping concentration can be obtained compared to the SD device without side high-k dielectric.…”

Numerical Analysis of the LDMOS With Side Triangular Field Plate

“…The side field plates are fabricated into the dielectric pillars to isolate from the silicon region. The electric field and doping concentration of the proposed STFP-LDMOS have been modulated by not only the side triangular field plates, but also the dielectric pillars [10]- [12]. Therefore, the BV and R on,sp have been significantly improved.…”